RV_TIMER Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.020s		1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.890s		1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.710s		1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.440s		1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.960s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.060s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.710s		1	1	100.00
		rv_timer_csr_aliasing	0.960s		1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.830s		0	1	0.00
V2	disabled	rv_timer_disabled	1.580s		1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	50.700s		1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	50.700s		1	1	100.00
V2	stress	rv_timer_stress_all	4.810s		1	1	100.00
V2	alert_test	rv_timer_alert_test	0.570s		1	1	100.00
V2	intr_test	rv_timer_intr_test	0.800s		1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.880s		1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.880s		1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.890s		1	1	100.00
		rv_timer_csr_rw	0.710s		1	1	100.00
		rv_timer_csr_aliasing	0.960s		1	1	100.00
		rv_timer_same_csr_outstanding	0.680s		1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.890s		1	1	100.00
		rv_timer_csr_rw	0.710s		1	1	100.00
		rv_timer_csr_aliasing	0.960s		1	1	100.00
		rv_timer_same_csr_outstanding	0.680s		1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.870s		1	1	100.00
		rv_timer_tl_intg_err	1.430s		1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.880s		0	1	0.00
V3	max_value	rv_timer_max	0.760s		0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.250s		1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.92108087731452223497231282582298616055197619681623590316477489174006687551526
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  91485944 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd879ab04) == 0x1
        UVM_INFO @  91485944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.90014674368523990370297331066007712995110972191605798699087197837124890992534
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 102831313 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x81a41b04) == 0x1
        UVM_INFO @ 102831313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.92627985687015013718746610852888619363459525222587873252702431104949965066393
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 897378722 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 897378722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---