SPI_DEVICE/1R1W Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	19.670s		1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.500s		1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.090s		1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.780s		1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.040s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.830s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.090s		1	1	100.00
		spi_device_csr_aliasing	16.040s		1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.900s		1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.920s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.860s		1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.720s		0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s		0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.840s		1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.840s		1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.690s		1	1	100.00
		spi_device_tpm_sts_read	0.930s		1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.540s		1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	17.540s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	17.540s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.660s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.550s		1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.020s		1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.020s		1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.020s		1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.120s		1	1	100.00
		spi_device_read_buffer_direct	2.600s		1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.020s		1	1	100.00
		spi_device_flash_all	16.350s		1	1	100.00
V2	quad_spi	spi_device_flash_all	16.350s		1	1	100.00
V2	dual_spi	spi_device_flash_all	16.350s		1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.570s		1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.570s		1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	19.670s		1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	25.890s		1	1	100.00
V2	stress_all	spi_device_stress_all	3.382m		1	1	100.00
V2	alert_test	spi_device_alert_test	0.910s		1	1	100.00
V2	intr_test	spi_device_intr_test	0.710s		1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.460s		1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.460s		1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.500s		1	1	100.00
		spi_device_csr_rw	1.090s		1	1	100.00
		spi_device_csr_aliasing	16.040s		1	1	100.00
		spi_device_same_csr_outstanding	2.120s		1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.500s		1	1	100.00
		spi_device_csr_rw	1.090s		1	1	100.00
		spi_device_csr_aliasing	16.040s		1	1	100.00
		spi_device_same_csr_outstanding	2.120s		1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.240s		1	1	100.00
		spi_device_tl_intg_err	14.850s		1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.850s		1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	37.700s		1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.107622276148087197709515084381752552690945328879233625427551353212552527005180
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2054723 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[105])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2054723 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2054723 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1001])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.50277796816411666516228366472192849764018704509139425325901458046269792045124
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    695684 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x814f32 [100000010100111100110010] vs 0x0 [0])
        UVM_ERROR @    769684 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a8ca2 [1010101000110010100010] vs 0x0 [0])
        UVM_ERROR @    852684 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd57833 [110101010111100000110011] vs 0x0 [0])
        UVM_ERROR @    937684 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x100d61 [100000000110101100001] vs 0x0 [0])
        UVM_ERROR @    980684 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xabb842 [101010111011100001000010] vs 0x0 [0])