SPI_DEVICE/2P Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	57.720s		1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.130s		1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.320s		1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.430s		1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.320s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.430s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.320s		1	1	100.00
		spi_device_csr_aliasing	12.320s		1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.920s		1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.290s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.040s		1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.130s		1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s		1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.170s		1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.170s		1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.740s		1	1	100.00
		spi_device_tpm_sts_read	0.900s		1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.620s		1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.330s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.610s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.610s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_read_status	spi_device_intercept	17.040s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	17.040s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	17.040s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_fast_read	spi_device_intercept	17.040s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	17.040s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.490s		1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.350s		1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.350s		1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.350s		1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.370s		1	1	100.00
		spi_device_read_buffer_direct	4.250s		1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.350s		1	1	100.00
		spi_device_flash_all	24.810s		1	1	100.00
V2	quad_spi	spi_device_flash_all	24.810s		1	1	100.00
V2	dual_spi	spi_device_flash_all	24.810s		1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.060s		1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.060s		1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	57.720s		1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.492m		1	1	100.00
V2	stress_all	spi_device_stress_all	4.211m		1	1	100.00
V2	alert_test	spi_device_alert_test	1.010s		1	1	100.00
V2	intr_test	spi_device_intr_test	1.040s		1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.100s		1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.100s		1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.130s		1	1	100.00
		spi_device_csr_rw	1.320s		1	1	100.00
		spi_device_csr_aliasing	12.320s		1	1	100.00
		spi_device_same_csr_outstanding	1.600s		1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.130s		1	1	100.00
		spi_device_csr_rw	1.320s		1	1	100.00
		spi_device_csr_aliasing	12.320s		1	1	100.00
		spi_device_same_csr_outstanding	1.600s		1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.530s		1	1	100.00
		spi_device_tl_intg_err	6.660s		1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.660s		1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.196m		1	1	100.00
		TOTAL			33	33	100.00