SPI_HOST Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.350m	19.025ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	29.420us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	18.579us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	140.687us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	91.057us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	63.519us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	18.579us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.057us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.447us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	56.054us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	9.000s	20.325us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	10.000s	116.447us	1	1	100.00
		spi_host_error_cmd	8.000s	22.156us	1	1	100.00
		spi_host_event	36.000s	1.381ms	1	1	100.00
V2	clock_rate	spi_host_speed	10.000s	23.969us	1	1	100.00
V2	speed	spi_host_speed	10.000s	23.969us	1	1	100.00
V2	chip_select_timing	spi_host_speed	10.000s	23.969us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	56.508us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	23.562us	1	1	100.00
V2	cpol_cpha	spi_host_speed	10.000s	23.969us	1	1	100.00
V2	full_cycle	spi_host_speed	10.000s	23.969us	1	1	100.00
V2	duplex	spi_host_smoke	1.350m	19.025ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.350m	19.025ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	458.459us	1	1	100.00
V2	spien	spi_host_spien	2.583m	20.811ms	1	1	100.00
V2	stall	spi_host_status_stall	9.000s	697.141us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	136.036us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	10.000s	116.447us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	19.121us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	17.728us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.000s	64.648us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.000s	64.648us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	29.420us	1	1	100.00
		spi_host_csr_rw	1.000s	18.579us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.057us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	30.871us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	29.420us	1	1	100.00
		spi_host_csr_rw	1.000s	18.579us	1	1	100.00
		spi_host_csr_aliasing	1.000s	91.057us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	30.871us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	98.993us	1	1	100.00
		spi_host_sec_cm	2.000s	266.794us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	98.993us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.350m	48.043ms	1	1	100.00
		TOTAL			26	26	100.00