| V1 |
smoke |
sysrst_ctrl_smoke |
5.630s |
|
1 |
1 |
100.00 |
| V1 |
input_output_inverted |
sysrst_ctrl_in_out_inverted |
6.720s |
|
1 |
1 |
100.00 |
| V1 |
combo_detect_ec_rst |
sysrst_ctrl_combo_detect_ec_rst |
1.370s |
|
1 |
1 |
100.00 |
| V1 |
combo_detect_ec_rst_with_pre_cond |
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond |
1.670s |
|
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
sysrst_ctrl_csr_hw_reset |
12.430s |
|
1 |
1 |
100.00 |
| V1 |
csr_rw |
sysrst_ctrl_csr_rw |
6.340s |
|
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
sysrst_ctrl_csr_bit_bash |
30.860s |
|
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
sysrst_ctrl_csr_aliasing |
2.960s |
|
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
sysrst_ctrl_csr_mem_rw_with_rand_reset |
2.740s |
|
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
sysrst_ctrl_csr_rw |
6.340s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_csr_aliasing |
2.960s |
|
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
9 |
9 |
100.00 |
| V2 |
combo_detect |
sysrst_ctrl_combo_detect |
2.306m |
|
1 |
1 |
100.00 |
| V2 |
combo_detect_with_pre_cond |
sysrst_ctrl_combo_detect_with_pre_cond |
1.135m |
|
1 |
1 |
100.00 |
| V2 |
auto_block_key_outputs |
sysrst_ctrl_auto_blk_key_output |
4.750s |
|
1 |
1 |
100.00 |
| V2 |
keyboard_input_triggered_interrupt |
sysrst_ctrl_edge_detect |
5.320s |
|
1 |
1 |
100.00 |
| V2 |
pin_output_keyboard_inversion_control |
sysrst_ctrl_pin_override_test |
5.110s |
|
1 |
1 |
100.00 |
| V2 |
pin_input_value_accessibility |
sysrst_ctrl_pin_access_test |
5.320s |
|
1 |
1 |
100.00 |
| V2 |
ec_power_on_reset |
sysrst_ctrl_ec_pwr_on_rst |
4.560s |
|
1 |
1 |
100.00 |
| V2 |
flash_write_protect_output |
sysrst_ctrl_flash_wr_prot_out |
1.970s |
|
1 |
1 |
100.00 |
| V2 |
ultra_low_power_test |
sysrst_ctrl_ultra_low_pwr |
1.210s |
|
1 |
1 |
100.00 |
| V2 |
sysrst_ctrl_feature_disable |
sysrst_ctrl_feature_disable |
38.260s |
|
1 |
1 |
100.00 |
| V2 |
stress_all |
sysrst_ctrl_stress_all |
11.090s |
|
1 |
1 |
100.00 |
| V2 |
alert_test |
sysrst_ctrl_alert_test |
2.290s |
|
1 |
1 |
100.00 |
| V2 |
intr_test |
sysrst_ctrl_intr_test |
3.490s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
sysrst_ctrl_tl_errors |
2.420s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
sysrst_ctrl_tl_errors |
2.420s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
sysrst_ctrl_csr_hw_reset |
12.430s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_csr_rw |
6.340s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_csr_aliasing |
2.960s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_same_csr_outstanding |
4.770s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
sysrst_ctrl_csr_hw_reset |
12.430s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_csr_rw |
6.340s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_csr_aliasing |
2.960s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_same_csr_outstanding |
4.770s |
|
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
sysrst_ctrl_sec_cm |
49.080s |
|
1 |
1 |
100.00 |
|
|
sysrst_ctrl_tl_intg_err |
53.590s |
|
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
sysrst_ctrl_tl_intg_err |
53.590s |
|
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
stress_all_with_rand_reset |
sysrst_ctrl_stress_all_with_rand_reset |
14.940s |
|
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
27 |
27 |
100.00 |