CHIP Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: `3c586cb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.344m	1	1	100.00
		chip_sw_example_rom	58.150s	1	1	100.00
		chip_sw_example_manufacturer	1.491m	1	1	100.00
		chip_sw_example_concurrency	2.087m	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.353m	1	1	100.00
V1	csr_rw	chip_csr_rw	3.492m	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	11.174m	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.336m	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	44.470s	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.336m	1	1	100.00
		chip_csr_rw	3.492m	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.450s	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.434m	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.434m	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.434m	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.438m	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.438m	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.330m	1	1	100.00
		chip_sw_uart_tx_rx_idx2	7.168m	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.684m	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.299m	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.955m	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.940m	1	1	100.00
V1		TOTAL		17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.384m	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.384m	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.060m	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.142m	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.902m	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.273m	1	1	100.00
		chip_tap_straps_testunlock0	5.913m	1	1	100.00
		chip_tap_straps_rma	7.133m	1	1	100.00
		chip_tap_straps_prod	1.616m	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.677m	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.537m	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.556m	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.556m	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.102m	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	31.502m	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.748m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.133m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.649m	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.033m	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.557m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.729m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.412m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.669m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.354m	1	1	100.00
		chip_sw_clkmgr_jitter	2.945m	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.167m	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.199m	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.345m	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.169m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.345m	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.843m	1	1	100.00
		chip_sw_aes_smoketest	2.741m	1	1	100.00
		chip_sw_aon_timer_smoketest	2.528m	1	1	100.00
		chip_sw_clkmgr_smoketest	2.000m	1	1	100.00
		chip_sw_csrng_smoketest	2.357m	1	1	100.00
		chip_sw_entropy_src_smoketest	15.423m	1	1	100.00
		chip_sw_gpio_smoketest	2.947m	1	1	100.00
		chip_sw_hmac_smoketest	3.239m	1	1	100.00
		chip_sw_kmac_smoketest	3.304m	1	1	100.00
		chip_sw_otbn_smoketest	20.006m	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.625m	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.583m	1	1	100.00
		chip_sw_rv_plic_smoketest	3.036m	1	1	100.00
		chip_sw_rv_timer_smoketest	1.793m	1	1	100.00
		chip_sw_rstmgr_smoketest	1.488m	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.916m	1	1	100.00
		chip_sw_uart_smoketest	1.730m	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.889m	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.307m	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.134h	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.919m	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.275m	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.558m	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.806m	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.986h	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.059h	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.850s	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.850s	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.336m	1	1	100.00
		chip_same_csr_outstanding	41.594m	1	1	100.00
		chip_csr_hw_reset	2.353m	1	1	100.00
		chip_csr_rw	3.492m	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.336m	1	1	100.00
		chip_same_csr_outstanding	41.594m	1	1	100.00
		chip_csr_hw_reset	2.353m	1	1	100.00
		chip_csr_rw	3.492m	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	24.560s	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.350s	1	1	100.00
		xbar_smoke_large_delays	1.177m	1	1	100.00
		xbar_smoke_slow_rsp	43.840s	1	1	100.00
		xbar_random_zero_delays	12.060s	1	1	100.00
		xbar_random_large_delays	4.870m	1	1	100.00
		xbar_random_slow_rsp	2.901m	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	5.460s	1	1	100.00
		xbar_error_and_unmapped_addr	34.030s	1	1	100.00
V2	xbar_error_cases	xbar_error_random	25.380s	1	1	100.00
		xbar_error_and_unmapped_addr	34.030s	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	22.170s	1	1	100.00
		xbar_access_same_device_slow_rsp	5.913m	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.400s	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.764m	1	1	100.00
		xbar_stress_all_with_error	5.477m	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.926m	1	1	100.00
		xbar_stress_all_with_reset_error	9.820s	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.919m	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.502m	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.594m	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.437m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.050m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.480m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.375m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.406m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.650s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.960s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.330s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.140s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.760s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.690s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	21.870s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	18.100s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	21.200s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.100s	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.220s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.280s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.060s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.960s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.930s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	21.860s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.200s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.640s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.500s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.780s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.100s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.070s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	21.080s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.960s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.040s	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.048m	1	1	100.00
		rom_e2e_asm_init_dev	41.794m	1	1	100.00
		rom_e2e_asm_init_prod	41.450m	1	1	100.00
		rom_e2e_asm_init_prod_end	41.786m	1	1	100.00
		rom_e2e_asm_init_rma	39.378m	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.772m	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.411m	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.379m	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.208m	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.555m	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.555m	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.202m	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.033m	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.296m	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.568m	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.248m	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.327m	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.036m	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.016m	1	1	100.00
		chip_plic_all_irqs_10	3.869m	1	1	100.00
		chip_plic_all_irqs_20	5.639m	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.600m	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.654m	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.159m	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.371m	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.812m	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.146m	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.515m	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.276h	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.341m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.625m	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.341m	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.505m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.505m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.428m	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.421m	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.281m	1	1	100.00
		chip_sw_aes_idle	2.568m	1	1	100.00
		chip_sw_hmac_enc_idle	2.309m	1	1	100.00
		chip_sw_kmac_idle	1.976m	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.883m	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.215m	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.344m	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.350m	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.799m	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.330m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.526m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.877m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.616m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.654m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.745m	1	1	100.00
		chip_sw_ast_clk_outputs	10.102m	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.300m	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.877m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.616m	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.748m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.133m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.649m	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.033m	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.557m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.729m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.412m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.669m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.354m	1	1	100.00
		chip_sw_clkmgr_jitter	2.945m	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.562m	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.038m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.046m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.129m	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.135m	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.507m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.729m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.322m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.460m	1	1	100.00
		chip_sw_flash_init_reduced_freq	21.309m	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	30.926m	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.102m	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.416m	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.473m	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.812m	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.162m	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.274m	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.782m	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.465m	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	27.083m	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.789m	1	1	100.00
		chip_sw_edn_entropy_reqs	12.597m	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.789m	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.162m	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.893m	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	21.668m	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.452m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.133m	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.726m	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.748m	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.080h	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	21.668m	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.805m	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.080h	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.869m	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.760m	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.820m	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.820m	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.265m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.729m	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.309m	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	18.227m	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.045m	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.356m	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.768m	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.836m	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.202m	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.412m	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	20.956m	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.248m	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.132m	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.725m	1	1	100.00
		chip_sw_kmac_mode_kmac	2.358m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.669m	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.171m	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.380m	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.976m	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.036m	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.273m	1	1	100.00
		chip_tap_straps_rma	7.133m	1	1	100.00
		chip_tap_straps_prod	1.616m	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.613m	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	30.162m	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.274m	1	1	100.00
		chip_sw_flash_rma_unlocked	1.080h	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.177m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.427m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.261m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.830m	0	1	0.00
		chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
		chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.798m	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.117m	1	1	100.00
		chip_prim_tl_access	2.869m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.300m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.330m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.526m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.877m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.616m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.654m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.745m	1	1	100.00
		chip_tap_straps_dev	1.273m	1	1	100.00
		chip_tap_straps_rma	7.133m	1	1	100.00
		chip_tap_straps_prod	1.616m	1	1	100.00
		chip_rv_dm_lc_disabled	2.532m	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.493m	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.642m	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.498m	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.547m	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.677m	1	1	100.00
		chip_rv_dm_lc_disabled	2.532m	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.091h	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.070h	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.281m	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.001h	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.677m	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.046m	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.064m	1	1	100.00
		rom_volatile_raw_unlock	1.034m	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.854m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.649m	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.281m	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.281m	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.281m	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.949m	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	21.668m	1	1	100.00
		chip_sw_otbn_mem_scramble	4.949m	1	1	100.00
		chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.026m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.926m	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	21.668m	1	1	100.00
		chip_sw_otbn_mem_scramble	4.949m	1	1	100.00
		chip_sw_keymgr_key_derivation	25.908m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.026m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.926m	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.263m	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.613m	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.177m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.427m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.261m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.830m	0	1	0.00
		chip_sw_lc_ctrl_transition	9.195m	1	1	100.00
		chip_prim_tl_access	2.869m	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.869m	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.640m	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.156m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.835m	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.381m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.242m	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	8.139m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.463m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	5.882m	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	9.505m	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.261m	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.277m	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.156m	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.070m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	40.647m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.319m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.538m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	8.012m	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.139m	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.918m	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.114m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.697m	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.798m	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.798m	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.918m	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	8.012m	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	6.277m	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.625m	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.968m	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.456m	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.596m	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.654m	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.043m	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.146m	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.806m	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.111m	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.008m	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.926m	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.456m	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.456m	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	21.545m	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.837m	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.968m	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.452m	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.848m	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.133m	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.532m	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.016m	1	1	100.00
		chip_plic_all_irqs_10	3.869m	1	1	100.00
		chip_plic_all_irqs_20	5.639m	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.812m	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.143m	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.919m	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.471m	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.511m	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.034m	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.759m	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.026m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.354m	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.298m	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.567m	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.117m	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	3.149m	0	1	0.00
		chip_sw_data_integrity_escalation	5.556m	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.139m	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.173m	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.767m	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.683m	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.347m	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.173m	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.173m	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	43.691m	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	43.691m	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.307m	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.555m	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.756m	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.173m	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.417m	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.911m	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.254m	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.431h	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.947m	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.874m	1	1	100.00
V2		TOTAL		233	275	84.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.096m	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.480m	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.569h	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.753m	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.783m	0	1	0.00
		rom_e2e_jtag_debug_dev	2.703m	0	1	0.00
		rom_e2e_jtag_debug_rma	10.477m	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.461m	1	1	100.00
		rom_e2e_jtag_inject_dev	2.925m	1	1	100.00
		rom_e2e_jtag_inject_rma	3.127m	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.087s	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.694m	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.999m	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	7.676m	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	20.968m	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.201m	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	10.369m	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	52.480s	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.761m	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.613m	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.251m	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.918m	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.783m	0	1	0.00
		rom_e2e_jtag_debug_dev	2.703m	0	1	0.00
		rom_e2e_jtag_debug_rma	10.477m	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.066m	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	3.149m	0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.538h	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.538h	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.884m	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.438m	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.735m	1	1	100.00
V3		TOTAL		18	23	78.26
	Unmapped tests	chip_sival_flash_info_access	2.544m	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.859m	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	34.120m	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.580m	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.210m	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.459m	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.818s	0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.961m	1	1	100.00
		TOTAL		276	326	84.66

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.35349143844384441168425393525634051673012885189679585367259359747069560834615
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.27140516319326412956152227785148113044181835037524830862737182545754911110590
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.93435094131018093169509320986248758815420245717742143750519448171485312844699
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.106504258933032859308442070054785761515850185371128877393922499681087040293322
    Line 548, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.79463851780801273159308864839740438292583853182706406170897522518893610032447
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.100303330557532624889415051491230974326503369916202212205210193139755804771917
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.88166118976912445373583522045089615561030783164345133168532698544440098182036
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.22324675874124250608707191728494345109997627240230967397094572037250526140124
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.85533633774196988544389976787695763395715520339858223953177147242561630038982
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.21818864828049719183969668138844226242398201386391452583009425517273538163340
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.8537194712771231993122580226547172668533369932494995616909316620423949441285
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.59629842193547617236678421524793052059702135980262398310121407176014590155946
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.79304594519567332894707827936581128324110083859004295331252303678883826336337
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.31109163027817405817090203496828527179768855112264900323965845319390529143514
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3357.146520 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3357.146520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.53655760324286462760163169085555945630816643047923297314784738209330134749327
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2279.886816 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2279.886816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 2 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.60326316705090420331750655427231630772610762003859391547764158875790945114138
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12444.246000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12444.246000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.53655119399774037484188104933550461993321708283010723878621120067701667169160
    Line 421, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 9488.727000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 9488.727000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.70735413667892588879067228983361107650432837222622862554730888996873164508029
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.102171158593637799808813939260054215938395787320183762254029528546029681034868
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.23178209296794932914925911424952397410336245543119747010808518735262909909576
    Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.40605451542633739203357125761525558484185597581437565936755020055092146182257
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.46707301723969216580557016651658666791755561093187909326675290696752614247315
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.66859687245852633484967669389507548665144411154547772690707143404806969653561
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 2 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.29585724107939759829588727615371637651025792903828199389146662929888156350881
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 4657.539717 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4657.539717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.114659788126509927964044317180921794015145930870740231418776739823009528985992
    Line 439, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3833.074600 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3833.074600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.64213924740707724970335747696629161363438798570748132009209333755669654862518
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2915.619036 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2915.619036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.94005770541121550976067324468172954138674388314516876136429830001976029552555
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3408.071000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3408.071000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.19396820549319706353702504543023701160368494102153108070987842762080284572385
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3034.514750 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3034.514750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.11657360001776681322473959603870531896860881806553990210768760738264288203544
    Line 430, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 5700.801890 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 5700.801890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.95307243107511386076324548427655798207352229584475092749668876808331006597496
    Line 455, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 26227.712751 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 26227.712751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78294) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.90578013781721084865837525345760175189935683124305444977865162141267952193652
Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4195.219800 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78294) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4195.219800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.111052931506960507451802649953441059457837999128994456321579583001746477627488
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35074.722215 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35074.722215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.24200993704367430171286002254469040743674125429294736237224584157151821935059
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3058.378628 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 52!
  UVM_INFO @ 3058.378628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.28069912953558427184330399820875659964693231012637185395846172197520403726263
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2946.397680 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2946.397680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.9189972383030415411888159519559016303512157008297870135490764778170617791036
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37412) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.45640822493969103464067810590047437600323767533710213929047758631431209658645
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2619.619536 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37412) { a_addr: 'h10584  a_data: 'h2ada307b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h1aee7  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2619.619536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.63091581793129293499016911299011526578175525541836044570885184490279404303031
    Line 232, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 6161.085975 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10678 read out mismatch
  UVM_INFO @ 6161.085975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.27782588489417848307373360235160788427236982873074016311646107634874926790652
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3720.116000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3720.116000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.65514122239413256880466163178073067734823408829266684206990371317616914465371
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2889.078000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2889.078000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.80250436739201007853807898538692134560413922409523299288197394181213579779353
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18951.257064 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18951.257064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.58856832388840008683370174647582023976866144150186474519679523270173872557847
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.115498828139317687118846482918296260536228668155014733844675228850379469413223
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.92755043431028725607441252500993765290129542251715984599743917699455422799865
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 13563.364476 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13563.364476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31792) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.83082117678009662192083134575294591319798707998004191168364328244125008706476
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2087.537000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31792) { a_addr: 'h107b4  a_data: 'h4cf8a7c8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h19981  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2087.537000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---