CHIP Simulation Results

Tuesday November 11 2025 17:32:35 UTC

GitHub Revision: b700cc2

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	116.23	0.0	1	1	100.00
		chip_sw_example_rom	81.11	0.0	1	1	100.00
		chip_sw_example_manufacturer	123.91000000000001	0.0	1	1	100.00
		chip_sw_example_concurrency	170.51	0.0	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	180.95	0.0	1	1	100.00
V1	csr_rw	chip_csr_rw	457.48	0.0	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	497.11	0.0	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	4150.57	0.0	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	65.82	0.0	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	4150.57	0.0	1	1	100.00
		chip_csr_rw	457.48	0.0	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.92	0.0	3	3	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	267.72	0.0	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	267.72	0.0	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	267.72	0.0	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	333.81	0.0	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	333.81	0.0	1	1	100.00
		chip_sw_uart_tx_rx_idx1	345.29	0.0	1	1	100.00
		chip_sw_uart_tx_rx_idx2	402.05	0.0	1	1	100.00
		chip_sw_uart_tx_rx_idx3	353.37	0.0	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1107.28	0.0	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	318.36	0.0	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	265.55	0.0	1	1	100.00
V1		TOTAL			19	20	95.00
V2	chip_pin_mux	chip_padctrl_attributes	152.78	0.0	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	152.78	0.0	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	139.23	0.0	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	127.6	0.0	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	199.8	0.0	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	961.11	0.0	1	1	100.00
		chip_tap_straps_testunlock0	375.92	0.0	1	1	100.00
		chip_tap_straps_rma	195.45	0.0	1	1	100.00
		chip_tap_straps_prod	1277.94	0.0	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	171.56	0.0	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	891.04	0.0	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	425.57	0.0	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	425.57	0.0	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	495.59999999999997	0.0	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	1672.22	0.0	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	333.97	0.0	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	612.57	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3465.8	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en	161.59	0.0	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	549.61	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en	171.56	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	588.8	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.55	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	258.24	0.0	1	1	100.00
		chip_sw_clkmgr_jitter	179.89	0.0	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	171.56	0.0	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	607.0	0.0	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	281.97	0.0	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	120.98999999999998	0.0	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	281.97	0.0	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	141.15	0.0	1	1	100.00
		chip_sw_aes_smoketest	186.53	0.0	1	1	100.00
		chip_sw_aon_timer_smoketest	233.5	0.0	1	1	100.00
		chip_sw_clkmgr_smoketest	154.96	0.0	1	1	100.00
		chip_sw_csrng_smoketest	108.43	0.0	1	1	100.00
		chip_sw_entropy_src_smoketest	668.02	0.0	1	1	100.00
		chip_sw_gpio_smoketest	154.89	0.0	1	1	100.00
		chip_sw_hmac_smoketest	222.15	0.0	1	1	100.00
		chip_sw_kmac_smoketest	158.02	0.0	1	1	100.00
		chip_sw_otbn_smoketest	1133.59	0.0	1	1	100.00
		chip_sw_pwrmgr_smoketest	173.89	0.0	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	227.19	0.0	1	1	100.00
		chip_sw_rv_plic_smoketest	129.71	0.0	1	1	100.00
		chip_sw_rv_timer_smoketest	134.51	0.0	1	1	100.00
		chip_sw_rstmgr_smoketest	118.63	0.0	1	1	100.00
		chip_sw_sram_ctrl_smoketest	114.45	0.0	1	1	100.00
		chip_sw_uart_smoketest	163.69	0.0	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	121.14999999999999	0.0	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	379.73	0.0	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7869.840000000001	0.0	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2633.33	0.0	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	817.46	0.0	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	231.08	0.0	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	171.49	0.0	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	7355.62	0.0	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	7517.270000000001	0.0	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	54.78	0.0	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	54.78	0.0	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	4150.57	0.0	1	1	100.00
		chip_same_csr_outstanding	1522.53	0.0	1	1	100.00
		chip_csr_hw_reset	180.95	0.0	1	1	100.00
		chip_csr_rw	457.48	0.0	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	4150.57	0.0	1	1	100.00
		chip_same_csr_outstanding	1522.53	0.0	1	1	100.00
		chip_csr_hw_reset	180.95	0.0	1	1	100.00
		chip_csr_rw	457.48	0.0	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	43.91	0.0	3	3	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.88	0.0	3	3	100.00
		xbar_smoke_large_delays	50.29	0.0	3	3	100.00
		xbar_smoke_slow_rsp	36.29	0.0	3	3	100.00
		xbar_random_zero_delays	16.73	0.0	3	3	100.00
		xbar_random_large_delays	77.54	0.0	3	3	100.00
		xbar_random_slow_rsp	54.62	0.0	3	3	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	21.2	0.0	3	3	100.00
		xbar_error_and_unmapped_addr	14.06	0.0	3	3	100.00
V2	xbar_error_cases	xbar_error_random	19.71	0.0	3	3	100.00
		xbar_error_and_unmapped_addr	14.06	0.0	3	3	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	39.45	0.0	3	3	100.00
		xbar_access_same_device_slow_rsp	163.34	0.0	3	3	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.42	0.0	3	3	100.00
V2	xbar_stress_all	xbar_stress_all	198.18	0.0	3	3	100.00
		xbar_stress_all_with_error	314.95	0.0	3	3	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	345.53	0.0	3	3	100.00
		xbar_stress_all_with_reset_error	273.04	0.0	3	3	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	2633.33	0.0	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	2449.06	0.0	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2524.54	0.0	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2138.51	0.0	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2718.64	0.0	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2804.93	0.0	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2734.61	0.0	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2580.77	0.0	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	22.53	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.99	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	22.45	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	23.11	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	22.82	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	20.64	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.22	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.79	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	29.76	0.0	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.59	0.0	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.31	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.56	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	19.82	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.9	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.76	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.8	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	20.11	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.47	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.51	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.51	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.02	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	21.0	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.56	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	22.25	0.0	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.03	0.0	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1977.1000000000001	0.0	1	1	100.00
		rom_e2e_asm_init_dev	2625.39	0.0	1	1	100.00
		rom_e2e_asm_init_prod	2441.22	0.0	1	1	100.00
		rom_e2e_asm_init_prod_end	2507.02	0.0	1	1	100.00
		rom_e2e_asm_init_rma	2425.22	0.0	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2383.23	0.0	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2364.42	0.0	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2348.57	0.0	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2627.86	0.0	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3310.74	0.0	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3310.74	0.0	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	173.99	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en	161.59	0.0	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	159.94	0.0	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	128.07	0.0	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	1377.73	0.0	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	177.81	0.0	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	332.19	0.0	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	506.43	0.0	1	1	100.00
		chip_plic_all_irqs_10	251.22999999999996	0.0	1	1	100.00
		chip_plic_all_irqs_20	407.1	0.0	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	186.64	0.0	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	1124.54	0.0	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	172.69	0.0	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	125.16	0.0	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	0.0	0.0	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	917.39	0.0	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	984.1700000000001	0.0	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	854.56	0.0	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7510.090000000001	0.0	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	263.72	0.0	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	173.89	0.0	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	263.72	0.0	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	349.02	0.0	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	349.02	0.0	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	262.1	0.0	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	324.44	0.0	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	653.66	0.0	1	1	100.00
		chip_sw_aes_idle	128.07	0.0	1	1	100.00
		chip_sw_hmac_enc_idle	171.18	0.0	1	1	100.00
		chip_sw_kmac_idle	166.05	0.0	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	178.16	0.0	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	196.35	0.0	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	237.32	0.0	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	200.44	0.0	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	753.2	0.0	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	351.61	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	368.34	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	388.91	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.18	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	408.65	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	339.43	0.0	1	1	100.00
		chip_sw_ast_clk_outputs	495.59999999999997	0.0	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	307.4	0.0	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	388.91	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.18	0.0	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	333.97	0.0	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	612.57	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3465.8	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en	161.59	0.0	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	549.61	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en	171.56	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	588.8	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.55	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	258.24	0.0	1	1	100.00
		chip_sw_clkmgr_jitter	179.89	0.0	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	147.17	0.0	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	343.31	0.0	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	636.74	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	2991.62	0.0	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	138.28	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	124.35	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1265.48	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	156.07	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	303.64	0.0	1	1	100.00
		chip_sw_flash_init_reduced_freq	1186.41	0.0	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13018.14	0.0	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	495.59999999999997	0.0	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	352.33	0.0	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	274.48	0.0	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	917.39	0.0	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	734.86	0.0	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	131.44	0.0	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	391.44	0.0	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	145.0	0.0	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	3376.09	0.0	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	188.78	0.0	1	1	100.00
		chip_sw_edn_entropy_reqs	724.71	0.0	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	188.78	0.0	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	734.86	0.0	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	92.57	0.0	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1152.22	0.0	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	552.02	0.0	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	612.57	0.0	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	309.95	0.0	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	333.97	0.0	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	3788.6599999999994	0.0	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1152.22	0.0	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	199.41	0.0	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	3788.6599999999994	0.0	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	209.27	0.0	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	546.56	0.0	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	460.65	0.0	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	460.65	0.0	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	140.49	0.0	1	1	100.00
		chip_sw_hmac_enc_jitter_en	171.56	0.0	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	171.18	0.0	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1059.39	0.0	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	312.37	0.0	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	435.98	0.0	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	428.86	0.0	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	364.21	0.0	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	327.07	0.0	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	588.8	0.0	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	829.62	0.0	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	1377.73	0.0	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2812.28	0.0	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	149.51	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac	146.51	0.0	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.55	0.0	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	148.72	0.0	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	934.14	0.0	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	166.05	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	332.19	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	961.11	0.0	1	1	100.00
		chip_tap_straps_rma	195.45	0.0	1	1	100.00
		chip_tap_straps_prod	1277.94	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	110.62	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	1382.73	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	209.27	0.0	1	1	100.00
		chip_rv_dm_lc_disabled	252.13999999999996	0.0	1	1	100.00
		chip_sw_flash_ctrl_lc_rw_en	319.65	0.0	1	1	100.00
		chip_sw_flash_rma_unlocked	3788.6599999999994	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	203.33	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	642.22	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	571.07	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	565.41	0.0	0	1	0.00
		chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	348.81	0.0	1	1	100.00
		chip_sw_sram_ctrl_execution_main	485.7099999999999	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	307.4	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	351.61	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	368.34	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	388.91	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.18	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	408.65	0.0	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	339.43	0.0	1	1	100.00
		chip_tap_straps_dev	961.11	0.0	1	1	100.00
		chip_tap_straps_rma	195.45	0.0	1	1	100.00
		chip_tap_straps_prod	1277.94	0.0	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	171.55	0.0	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	86.13	0.0	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	76.73	0.0	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	144.25	0.0	1	1	100.00
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	252.13999999999996	0.0	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1434.64	0.0	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3902.13	0.0	1	1	100.00
		chip_sw_lc_walkthrough_prod	4167.67	0.0	1	1	100.00
		chip_sw_lc_walkthrough_prodend	454.29	0.0	1	1	100.00
		chip_sw_lc_walkthrough_rma	3846.73	0.0	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1434.64	0.0	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	72.8	0.0	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.01	0.0	1	1	100.00
		rom_volatile_raw_unlock	73.17	0.0	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3278.94	0.0	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3465.8	0.0	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	653.66	0.0	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	653.66	0.0	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	653.66	0.0	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	283.98	0.0	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1152.22	0.0	1	1	100.00
		chip_sw_otbn_mem_scramble	283.98	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	433.77	0.0	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	150.04	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1152.22	0.0	1	1	100.00
		chip_sw_otbn_mem_scramble	283.98	0.0	1	1	100.00
		chip_sw_keymgr_key_derivation	913.44	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	433.77	0.0	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	150.04	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	322.06	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	110.62	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	209.27	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	203.33	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	642.22	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	571.07	0.0	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	565.41	0.0	0	1	0.00
		chip_sw_lc_ctrl_transition	724.2	0.0	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	209.27	0.0	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1080.62	0.0	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	303.13	0.0	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	975.2599999999999	0.0	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	225.77	0.0	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	317.68	0.0	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	437.08	0.0	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1116.51	0.0	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	485.11999999999995	0.0	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	349.02	0.0	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	632.16	0.0	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	307.64	0.0	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	303.13	0.0	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	276.2	0.0	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	187.21	0.0	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	285.59	0.0	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	244.28	0.0	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	143.42	0.0	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	520.12	0.0	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	708.35	0.0	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1388.92	0.0	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	177.74	0.0	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	348.81	0.0	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	348.81	0.0	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	708.35	0.0	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	143.42	0.0	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	307.64	0.0	1	1	100.00
		chip_sw_pwrmgr_smoketest	173.89	0.0	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	294.38	0.0	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	211.14	0.0	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	294.65	0.0	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	1124.54	0.0	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	140.67	0.0	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	984.1700000000001	0.0	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	459.66	0.0	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	474.95	0.0	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	192.36	0.0	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	150.04	0.0	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	211.14	0.0	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	211.14	0.0	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	1740.57	0.0	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1007.7200000000001	0.0	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	294.38	0.0	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	290.55	0.0	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	315.38	0.0	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	195.45	0.0	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	252.13999999999996	0.0	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	506.43	0.0	1	1	100.00
		chip_plic_all_irqs_10	251.22999999999996	0.0	1	1	100.00
		chip_plic_all_irqs_20	407.1	0.0	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	152.35	0.0	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	169.39	0.0	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2633.33	0.0	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	497.09	0.0	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	173.72	0.0	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	255.57	0.0	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	187.13	0.0	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	433.77	0.0	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	258.24	0.0	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	404.45	0.0	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	430.78	0.0	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	485.7099999999999	0.0	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
		chip_sw_data_integrity_escalation	425.57	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	520.12	0.0	1	1	100.00
		chip_sw_sysrst_ctrl_reset	1129.05	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	138.46	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	260.85	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	357.38	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	1129.05	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	1129.05	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2519.59	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2519.59	0.0	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	322.31	0.0	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3310.74	0.0	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	117.31	0.0	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	117.54	0.0	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	278.38	0.0	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	296.21	0.0	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	1020.74	0.0	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	4925.18	0.0	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1853.15	0.0	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	122.14	0.0	1	1	100.00
V2		TOTAL			266	309	86.08
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	146.18	0.0	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	94.81	0.0	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	9332.76	0.0	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1061.21	0.0	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1258.66	0.0	1	1	100.00
		rom_e2e_jtag_debug_dev	167.32	0.0	0	1	0.00
		rom_e2e_jtag_debug_rma	191.33	0.0	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	165.28	0.0	1	1	100.00
		rom_e2e_jtag_inject_dev	246.85	0.0	1	1	100.00
		rom_e2e_jtag_inject_rma	208.13	0.0	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.901773	0.0	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	483.64	0.0	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	282.2	0.0	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1079.54	0.0	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	791.07	0.0	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	197.8	0.0	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	559.03	0.0	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	89.56	0.0	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	146.83	0.0	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	257.1	0.0	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	295.19	0.0	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	708.35	0.0	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1258.66	0.0	1	1	100.00
		rom_e2e_jtag_debug_dev	167.32	0.0	0	1	0.00
		rom_e2e_jtag_debug_rma	191.33	0.0	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	349.88	0.0	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	197.39	0.0	0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	5370.45	0.0	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	5370.45	0.0	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	150.92	0.0	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	333.81	0.0	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	3098.97	0.0	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	prim_present_test	16.86	0.0	1	1	100.00
		i2c_tl_errors	1.42	0.0	1	1	100.00
		i2c_tl_intg_err	1.26	0.0	1	1	100.00
		i2c_intr_test	0.75	0.0	1	1	100.00
		i2c_csr_hw_reset	0.77	0.0	1	1	100.00
		i2c_csr_rw	0.87	0.0	1	1	100.00
		i2c_csr_bit_bash	1.9	0.0	1	1	100.00
		i2c_csr_aliasing	1.48	0.0	1	1	100.00
		i2c_same_csr_outstanding	0.94	0.0	1	1	100.00
		i2c_csr_mem_rw_with_rand_reset	0.96	0.0	1	1	100.00
		prim_async_alert	0.45	0.0	1	1	100.00
		prim_async_fatal_alert	0.53	0.0	1	1	100.00
		prim_async_fatal_alert_with_3_cycles_skew	0.43	0.0	1	1	100.00
		prim_sync_alert	0.44	0.0	1	1	100.00
		prim_sync_fatal_alert	0.42	0.0	1	1	100.00
		gpio_smoke	0.9	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown	0.84	0.0	1	1	100.00
		gpio_random_dout_din	0.79	0.0	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.06	0.0	1	1	100.00
		gpio_dout_din_regs_random_rw	0.73	0.0	1	1	100.00
		gpio_intr_rand_pgm	0.76	0.0	1	1	100.00
		gpio_rand_intr_trigger	1.83	0.0	1	1	100.00
		gpio_intr_with_filter_rand_intr_event	1.38	0.0	1	1	100.00
		gpio_filter_stress	11.31	0.0	1	1	100.00
		gpio_random_long_reg_writes_reg_reads	2.85	0.0	1	1	100.00
		gpio_full_random	0.68	0.0	1	1	100.00
		gpio_stress_all	38.96	0.0	1	1	100.00
		gpio_stress_all_with_rand_reset	1.51	0.0	0	1	0.00
		gpio_rand_straps	0.54	0.0	1	1	100.00
		gpio_sec_cm	0.8	0.0	1	1	100.00
		gpio_alert_test	0.55	0.0	1	1	100.00
		gpio_csr_rw	0.64	0.0	1	1	100.00
		gpio_same_csr_outstanding	0.61	0.0	1	1	100.00
		gpio_csr_aliasing	0.69	0.0	1	1	100.00
		gpio_csr_mem_rw_with_rand_reset	0.69	0.0	1	1	100.00
		gpio_tl_intg_err	1.13	0.0	1	1	100.00
		gpio_tl_errors	1.71	0.0	1	1	100.00
		gpio_intr_test	0.58	0.0	1	1	100.00
		gpio_csr_hw_reset	0.62	0.0	1	1	100.00
		gpio_csr_bit_bash	2.51	0.0	1	1	100.00
		gpio_smoke_en_cdc_prim	0.86	0.0	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	0.85	0.0	1	1	100.00
		adc_ctrl_smoke	9.94	0.0	1	1	100.00
		adc_ctrl_filters_polled	270.03	0.0	1	1	100.00
		adc_ctrl_filters_polled_fixed	315.56	0.0	1	1	100.00
		adc_ctrl_filters_interrupt	736.46	0.0	1	1	100.00
		adc_ctrl_filters_interrupt_fixed	101.24	0.0	1	1	100.00
		adc_ctrl_filters_wakeup	1074.77	0.0	1	1	100.00
		adc_ctrl_filters_wakeup_fixed	352.79	0.0	1	1	100.00
		adc_ctrl_clock_gating	285.77	0.0	1	1	100.00
		adc_ctrl_filters_both	867.94	0.0	1	1	100.00
		adc_ctrl_poweron_counter	2.56	0.0	1	1	100.00
		adc_ctrl_lowpower_counter	55.45	0.0	1	1	100.00
		adc_ctrl_fsm_reset	42.49	0.0	1	1	100.00
		adc_ctrl_stress_all_with_rand_reset	7.6	0.0	1	1	100.00
		adc_ctrl_stress_all	841.16	0.0	1	1	100.00
		adc_ctrl_sec_cm	8.14	0.0	1	1	100.00
		adc_ctrl_alert_test	0.87	0.0	1	1	100.00
		adc_ctrl_tl_errors	2.31	0.0	1	1	100.00
		adc_ctrl_tl_intg_err	4.06	0.0	1	1	100.00
		adc_ctrl_intr_test	0.91	0.0	1	1	100.00
		adc_ctrl_csr_hw_reset	2.01	0.0	1	1	100.00
		adc_ctrl_csr_rw	1.11	0.0	1	1	100.00
		adc_ctrl_csr_bit_bash	19.78	0.0	1	1	100.00
		adc_ctrl_csr_aliasing	2.14	0.0	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.76	0.0	1	1	100.00
		adc_ctrl_csr_mem_rw_with_rand_reset	1.18	0.0	1	1	100.00
		uart_smoke	2.06	0.0	1	1	100.00
		uart_tx_rx	18.8	0.0	1	1	100.00
		uart_fifo_full	40.36	0.0	1	1	100.00
		uart_fifo_overflow	5.8	0.0	1	1	100.00
		uart_fifo_reset	93.46	0.0	1	1	100.00
		uart_rx_oversample	7.9	0.0	1	1	100.00
		uart_intr	11.33	0.0	1	1	100.00
		uart_noise_filter	0.94	0.0	0	1	0.00
		uart_rx_start_bit_filter	5.32	0.0	1	1	100.00
		uart_rx_parity_err	8.04	0.0	1	1	100.00
		uart_tx_ovrd	13.48	0.0	1	1	100.00
		uart_loopback	5.42	0.0	1	1	100.00
		uart_perf	822.92	0.0	1	1	100.00
		uart_long_xfer_wo_dly	369.36	0.0	1	1	100.00
		uart_stress_all_with_rand_reset	14.61	0.0	1	1	100.00
		uart_stress_all	1046.7	0.0	1	1	100.00
		uart_sec_cm	0.75	0.0	1	1	100.00
		uart_alert_test	0.66	0.0	1	1	100.00
		uart_tl_errors	1.76	0.0	1	1	100.00
		uart_tl_intg_err	0.94	0.0	1	1	100.00
		uart_intr_test	0.65	0.0	1	1	100.00
		uart_csr_hw_reset	0.62	0.0	1	1	100.00
		uart_csr_rw	0.62	0.0	1	1	100.00
		uart_csr_bit_bash	1.78	0.0	1	1	100.00
		uart_csr_aliasing	0.68	0.0	1	1	100.00
		uart_same_csr_outstanding	0.63	0.0	1	1	100.00
		uart_csr_mem_rw_with_rand_reset	0.72	0.0	1	1	100.00
		keymgr_smoke	1.84	0.0	1	1	100.00
		keymgr_sideload	22.19	0.0	1	1	100.00
		keymgr_sideload_kmac	15.58	0.0	1	1	100.00
		keymgr_sideload_aes	2.41	0.0	1	1	100.00
		keymgr_sideload_otbn	3.37	0.0	1	1	100.00
		keymgr_random	3.41	0.0	1	1	100.00
		keymgr_cfg_regwen	1.83	0.0	1	1	100.00
		keymgr_direct_to_disabled	1.43	0.0	1	1	100.00
		keymgr_lc_disable	1.95	0.0	1	1	100.00
		keymgr_sw_invalid_input	3.08	0.0	1	1	100.00
		keymgr_hwsw_invalid_input	3.73	0.0	1	1	100.00
		keymgr_kmac_rsp_err	3.07	0.0	1	1	100.00
		keymgr_custom_cm	3.87	0.0	1	1	100.00
		keymgr_sideload_protect	2.2	0.0	1	1	100.00
		keymgr_sync_async_fault_cross	1.78	0.0	1	1	100.00
		keymgr_stress_all	26.86	0.0	1	1	100.00
		keymgr_stress_all_with_rand_reset	6.29	0.0	1	1	100.00
		keymgr_sec_cm	7.75	0.0	1	1	100.00
		keymgr_alert_test	0.68	0.0	1	1	100.00
		keymgr_shadow_reg_errors	1.44	0.0	1	1	100.00
		keymgr_shadow_reg_errors_with_csr_rw	6.3	0.0	1	1	100.00
		keymgr_tl_errors	1.78	0.0	1	1	100.00
		keymgr_tl_intg_err	4.67	0.0	1	1	100.00
		keymgr_intr_test	0.65	0.0	1	1	100.00
		keymgr_csr_hw_reset	0.85	0.0	1	1	100.00
		keymgr_csr_rw	0.84	0.0	1	1	100.00
		keymgr_csr_bit_bash	9.58	0.0	1	1	100.00
		keymgr_csr_aliasing	3.53	0.0	1	1	100.00
		keymgr_same_csr_outstanding	1.46	0.0	1	1	100.00
		keymgr_csr_mem_rw_with_rand_reset	1.14	0.0	1	1	100.00
		prim_lfsr_fib_test	156.0	0.0	1	1	100.00
		prim_lfsr_fib_smoke	1.35	0.0	1	1	100.00
		prim_lfsr_gal_test	154.02	0.0	1	1	100.00
		prim_lfsr_gal_smoke	1.3	0.0	1	1	100.00
		hmac_smoke	8.64	0.0	1	1	100.00
		hmac_long_msg	32.12	0.0	1	1	100.00
		hmac_stress_reset	2.69	0.0	1	1	100.00
		hmac_back_pressure	2.18	0.0	1	1	100.00
		hmac_datapath_stress	1107.24	0.0	1	1	100.00
		hmac_burst_wr	25.75	0.0	1	1	100.00
		hmac_error	34.51	0.0	1	1	100.00
		hmac_wipe_secret	5.11	0.0	1	1	100.00
		hmac_test_sha256_vectors	191.23	0.0	1	1	100.00
		hmac_test_sha384_vectors	407.44	0.0	1	1	100.00
		hmac_test_sha512_vectors	18.86	0.0	1	1	100.00
		hmac_test_hmac256_vectors	9.24	0.0	1	1	100.00
		hmac_test_hmac384_vectors	8.04	0.0	1	1	100.00
		hmac_test_hmac512_vectors	11.63	0.0	1	1	100.00
		hmac_stress_all	752.33	0.0	1	1	100.00
		hmac_stress_all_with_rand_reset	83.93	0.0	1	1	100.00
		hmac_directed	0.96	0.0	1	1	100.00
		hmac_sec_cm	0.94	0.0	1	1	100.00
		hmac_alert_test	0.57	0.0	1	1	100.00
		hmac_tl_errors	1.82	0.0	1	1	100.00
		hmac_tl_intg_err	2.79	0.0	1	1	100.00
		hmac_intr_test	0.61	0.0	1	1	100.00
		hmac_csr_hw_reset	0.85	0.0	1	1	100.00
		hmac_csr_rw	0.8	0.0	1	1	100.00
		hmac_csr_bit_bash	9.72	0.0	1	1	100.00
		hmac_csr_aliasing	2.17	0.0	1	1	100.00
		hmac_same_csr_outstanding	1.45	0.0	1	1	100.00
		hmac_csr_mem_rw_with_rand_reset	137.51	0.0	1	1	100.00
		spi_device_csb_read	0.81	0.0	2	2	100.00
		spi_device_mem_parity	1.02	0.0	1	2	50.00
		spi_device_ram_cfg	0.86	0.0	1	2	50.00
		spi_device_tpm_read_hw_reg	1.79	0.0	2	2	100.00
		spi_device_tpm_all	23.0	0.0	2	2	100.00
		spi_device_tpm_sts_read	0.82	0.0	2	2	100.00
		spi_device_tpm_rw	1.12	0.0	2	2	100.00
		spi_device_pass_cmd_filtering	6.82	0.0	2	2	100.00
		spi_device_pass_addr_payload_swap	7.38	0.0	2	2	100.00
		spi_device_intercept	16.28	0.0	2	2	100.00
		spi_device_mailbox	55.51	0.0	2	2	100.00
		spi_device_upload	5.56	0.0	2	2	100.00
		spi_device_cfg_cmd	11.26	0.0	2	2	100.00
		spi_device_flash_mode	18.26	0.0	1	2	50.00
		spi_device_flash_mode_ignore_cmds	248.12999999999997	0.0	2	2	100.00
		spi_device_read_buffer_direct	8.34	0.0	2	2	100.00
		spi_device_flash_all	58.59	0.0	2	2	100.00
		spi_device_flash_and_tpm	75.7	0.0	2	2	100.00
		spi_device_flash_and_tpm_min_idle	115.62	0.0	2	2	100.00
		spi_device_stress_all	120.34000000000002	0.0	2	2	100.00
		spi_device_sec_cm	1.41	0.0	2	2	100.00
		spi_device_alert_test	0.91	0.0	2	2	100.00
		spi_device_tl_errors	3.39	0.0	2	2	100.00
		spi_device_tl_intg_err	11.35	0.0	2	2	100.00
		spi_device_intr_test	0.87	0.0	2	2	100.00
		spi_device_mem_walk	0.66	0.0	2	2	100.00
		spi_device_mem_partial_access	1.8	0.0	2	2	100.00
		spi_device_csr_hw_reset	1.6	0.0	2	2	100.00
		spi_device_csr_rw	1.9	0.0	2	2	100.00
		spi_device_csr_bit_bash	23.67	0.0	2	2	100.00
		spi_device_csr_aliasing	14.6	0.0	2	2	100.00
		spi_device_same_csr_outstanding	3.13	0.0	2	2	100.00
		spi_device_csr_mem_rw_with_rand_reset	2.64	0.0	2	2	100.00
		rstmgr_smoke	1.07	0.0	1	1	100.00
		rstmgr_por_stretcher	0.9	0.0	1	1	100.00
		rstmgr_reset	3.19	0.0	1	1	100.00
		rstmgr_sw_rst_reset_race	0.91	0.0	1	1	100.00
		rstmgr_sw_rst	2.15	0.0	1	1	100.00
		rstmgr_sec_cm_scan_intersig_mubi	1.14	0.0	1	1	100.00
		rstmgr_leaf_rst_cnsty	6.36	0.0	1	1	100.00
		rstmgr_leaf_rst_shadow_attack	1.09	0.0	1	1	100.00
		rstmgr_stress_all	28.87	0.0	1	1	100.00
		rstmgr_sec_cm	20.6	0.0	1	1	100.00
		rstmgr_alert_test	0.86	0.0	1	1	100.00
		rstmgr_tl_errors	2.06	0.0	1	1	100.00
		rstmgr_tl_intg_err	1.99	0.0	1	1	100.00
		rstmgr_csr_hw_reset	1.19	0.0	1	1	100.00
		rstmgr_csr_rw	0.89	0.0	1	1	100.00
		rstmgr_csr_bit_bash	2.49	0.0	1	1	100.00
		rstmgr_csr_aliasing	1.29	0.0	1	1	100.00
		rstmgr_same_csr_outstanding	1.22	0.0	1	1	100.00
		rstmgr_csr_mem_rw_with_rand_reset	1.29	0.0	1	1	100.00
		prim_prince_test	9.75	0.0	1	1	100.00
		tl_agent_smoke	1.28	0.0	1	1	100.00
		clkmgr_smoke	1.09	0.0	1	1	100.00
		clkmgr_extclk	0.92	0.0	1	1	100.00
		clkmgr_frequency	6.7	0.0	1	1	100.00
		clkmgr_frequency_timeout	7.98	0.0	1	1	100.00
		clkmgr_peri	1.15	0.0	1	1	100.00
		clkmgr_trans	1.06	0.0	1	1	100.00
		clkmgr_clk_status	0.73	0.0	1	1	100.00
		clkmgr_idle_intersig_mubi	1.21	0.0	1	1	100.00
		clkmgr_lc_ctrl_intersig_mubi	0.98	0.0	1	1	100.00
		clkmgr_lc_clk_byp_req_intersig_mubi	0.82	0.0	1	1	100.00
		clkmgr_clk_handshake_intersig_mubi	0.78	0.0	1	1	100.00
		clkmgr_div_intersig_mubi	0.81	0.0	1	1	100.00
		clkmgr_regwen	2.89	0.0	1	1	100.00
		clkmgr_sec_cm	3.27	0.0	1	1	100.00
		clkmgr_stress_all_with_rand_reset	35.12	0.0	1	1	100.00
		clkmgr_stress_all	11.16	0.0	1	1	100.00
		clkmgr_alert_test	0.97	0.0	1	1	100.00
		clkmgr_shadow_reg_errors	1.61	0.0	1	1	100.00
		clkmgr_shadow_reg_errors_with_csr_rw	1.84	0.0	1	1	100.00
		clkmgr_tl_errors	1.83	0.0	1	1	100.00
		clkmgr_tl_intg_err	1.52	0.0	1	1	100.00
		clkmgr_csr_hw_reset	1.06	0.0	1	1	100.00
		clkmgr_csr_rw	0.91	0.0	1	1	100.00
		clkmgr_csr_bit_bash	3.12	0.0	1	1	100.00
		clkmgr_csr_aliasing	1.71	0.0	1	1	100.00
		clkmgr_same_csr_outstanding	1.22	0.0	1	1	100.00
		clkmgr_csr_mem_rw_with_rand_reset	0.96	0.0	1	1	100.00
		sysrst_ctrl_smoke	5.16	0.0	1	1	100.00
		sysrst_ctrl_in_out_inverted	5.82	0.0	1	1	100.00
		sysrst_ctrl_combo_detect_ec_rst	5.17	0.0	1	1	100.00
		sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.02	0.0	1	1	100.00
		sysrst_ctrl_pin_access_test	2.8	0.0	1	1	100.00
		sysrst_ctrl_pin_override_test	6.87	0.0	1	1	100.00
		sysrst_ctrl_flash_wr_prot_out	2.29	0.0	1	1	100.00
		sysrst_ctrl_ec_pwr_on_rst	2.3	0.0	1	1	100.00
		sysrst_ctrl_auto_blk_key_output	2.6	0.0	1	1	100.00
		sysrst_ctrl_ultra_low_pwr	4.83	0.0	1	1	100.00
		sysrst_ctrl_combo_detect	65.21	0.0	1	1	100.00
		sysrst_ctrl_edge_detect	3.42	0.0	1	1	100.00
		sysrst_ctrl_combo_detect_with_pre_cond	27.06	0.0	1	1	100.00
		sysrst_ctrl_feature_disable	13.65	0.0	1	1	100.00
		sysrst_ctrl_stress_all_with_rand_reset	7.03	0.0	1	1	100.00
		sysrst_ctrl_stress_all	5.26	0.0	1	1	100.00
		sysrst_ctrl_sec_cm	50.67	0.0	1	1	100.00
		sysrst_ctrl_alert_test	5.34	0.0	1	1	100.00
		sysrst_ctrl_tl_errors	2.14	0.0	1	1	100.00
		sysrst_ctrl_tl_intg_err	11.85	0.0	1	1	100.00
		sysrst_ctrl_intr_test	4.82	0.0	1	1	100.00
		sysrst_ctrl_csr_hw_reset	9.96	0.0	1	1	100.00
		sysrst_ctrl_csr_rw	2.05	0.0	1	1	100.00
		sysrst_ctrl_csr_bit_bash	66.73	0.0	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.78	0.0	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	3.55	0.0	1	1	100.00
		sysrst_ctrl_csr_mem_rw_with_rand_reset	4.74	0.0	1	1	100.00
		i2c_host_smoke	66.51	0.0	1	1	100.00
		i2c_host_override	0.64	0.0	1	1	100.00
		i2c_host_fifo_watermark	100.31	0.0	1	1	100.00
		i2c_host_fifo_overflow	27.84	0.0	1	1	100.00
		i2c_host_fifo_reset_fmt	1.22	0.0	1	1	100.00
		i2c_host_fifo_fmt_empty	3.57	0.0	1	1	100.00
		i2c_host_fifo_reset_rx	3.68	0.0	1	1	100.00
		i2c_host_fifo_full	76.45	0.0	1	1	100.00
		i2c_host_perf	573.74	0.0	1	1	100.00
		i2c_host_perf_precise	41.46	0.0	1	1	100.00
		i2c_host_stretch_timeout	6.95	0.0	1	1	100.00
		i2c_host_error_intr	0.85	0.0	0	1	0.00
		i2c_host_stress_all	461.86	0.0	1	1	100.00
		i2c_target_glitch	3.01	0.0	0	1	0.00
		i2c_target_smoke	23.56	0.0	1	1	100.00
		i2c_target_stress_wr	14.57	0.0	1	1	100.00
		i2c_target_stress_rd	9.58	0.0	1	1	100.00
		i2c_target_stretch	1.52	0.0	1	1	100.00
		i2c_target_intr_smoke	5.59	0.0	1	1	100.00
		i2c_target_intr_stress_wr	50.25	0.0	1	1	100.00
		i2c_target_timeout	6.48	0.0	1	1	100.00
		i2c_target_unexp_stop	1.49	0.0	0	1	0.00
		i2c_target_fifo_reset_acq	1.2	0.0	1	1	100.00
		i2c_target_fifo_reset_tx	0.76	0.0	1	1	100.00
		i2c_target_perf	3.41	0.0	1	1	100.00
		i2c_target_stress_all	186.82	0.0	1	1	100.00
		i2c_target_bad_addr	3.79	0.0	1	1	100.00
		i2c_target_hrst	1.63	0.0	1	1	100.00
		i2c_host_stress_all_with_rand_reset	6.19	0.0	0	1	0.00
		i2c_target_stress_all_with_rand_reset	3.26	0.0	0	1	0.00
		i2c_host_mode_toggle	0.81	0.0	0	1	0.00
		i2c_host_may_nack	10.59	0.0	1	1	100.00
		i2c_target_fifo_watermarks_acq	1.89	0.0	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.51	0.0	1	1	100.00
		i2c_target_tx_stretch_ctrl	14.76	0.0	1	1	100.00
		i2c_target_smbus_maxlen	2.12	0.0	1	1	100.00
		i2c_target_nack_acqfull	2.13	0.0	1	1	100.00
		i2c_target_nack_acqfull_addr	1.58	0.0	1	1	100.00
		i2c_target_nack_txstretch	1.84	0.0	0	1	0.00
		i2c_sec_cm	1.13	0.0	1	1	100.00
		i2c_alert_test	0.63	0.0	1	1	100.00
		flash_ctrl_smoke	68.21	0.0	1	1	100.00
		flash_ctrl_smoke_hw	9.19	0.0	1	1	100.00
		flash_ctrl_rand_ops	239.65	0.0	1	1	100.00
		flash_ctrl_sw_op	10.97	0.0	1	1	100.00
		flash_ctrl_host_dir_rd	21.48	0.0	1	1	100.00
		flash_ctrl_rd_buff_evict	71.02	0.0	1	1	100.00
		flash_ctrl_phy_arb	67.57	0.0	1	1	100.00
		flash_ctrl_hw_sec_otp	102.72	0.0	1	1	100.00
		flash_ctrl_erase_suspend	177.72	0.0	1	1	100.00
		flash_ctrl_hw_rma	1421.75	0.0	1	1	100.00
		flash_ctrl_hw_rma_reset	548.07	0.0	1	1	100.00
		flash_ctrl_otp_reset	39.26	0.0	1	1	100.00
		flash_ctrl_host_ctrl_arb	1243.22	0.0	1	1	100.00
		flash_ctrl_mp_regions	283.32	0.0	1	1	100.00
		flash_ctrl_fetch_code	14.72	0.0	1	1	100.00
		flash_ctrl_full_mem_access	1727.76	0.0	1	1	100.00
		flash_ctrl_error_prog_type	762.62	0.0	1	1	100.00
		flash_ctrl_error_prog_win	278.53	0.0	1	1	100.00
		flash_ctrl_error_mp	478.35	0.0	1	1	100.00
		flash_ctrl_invalid_op	38.75	0.0	1	1	100.00
		flash_ctrl_mid_op_rst	31.83	0.0	1	1	100.00
		flash_ctrl_wo	116.99	0.0	1	1	100.00
		flash_ctrl_write_word_sweep	6.62	0.0	1	1	100.00
		flash_ctrl_read_word_sweep	6.08	0.0	1	1	100.00
		flash_ctrl_ro	69.91	0.0	1	1	100.00
		flash_ctrl_rw	362.4	0.0	1	1	100.00
		flash_ctrl_read_word_sweep_serr	12.57	0.0	1	1	100.00
		flash_ctrl_ro_serr	81.44	0.0	1	1	100.00
		flash_ctrl_rw_serr	134.05	0.0	1	1	100.00
		flash_ctrl_serr_counter	43.07	0.0	1	1	100.00
		flash_ctrl_serr_address	48.85	0.0	1	1	100.00
		flash_ctrl_read_word_sweep_derr	11.93	0.0	1	1	100.00
		flash_ctrl_ro_derr	87.19	0.0	1	1	100.00
		flash_ctrl_rw_derr	147.0	0.0	1	1	100.00
		flash_ctrl_derr_detect	111.01	0.0	1	1	100.00
		flash_ctrl_oversize_error	114.59	0.0	1	1	100.00
		flash_ctrl_integrity	367.96	0.0	1	1	100.00
		flash_ctrl_intr_rd	82.28	0.0	1	1	100.00
		flash_ctrl_intr_wr	43.66	0.0	1	1	100.00
		flash_ctrl_intr_rd_slow_flash	131.42	0.0	1	1	100.00
		flash_ctrl_intr_wr_slow_flash	233.7	0.0	1	1	100.00
		flash_ctrl_prog_reset	5.46	0.0	1	1	100.00
		flash_ctrl_rw_evict	20.98	0.0	1	1	100.00
		flash_ctrl_rw_evict_all_en	13.62	0.0	1	1	100.00
		flash_ctrl_re_evict	19.46	0.0	1	1	100.00
		flash_ctrl_disable	9.96	0.0	1	1	100.00
		flash_ctrl_sec_cm	1510.96	0.0	1	1	100.00
		flash_ctrl_sec_info_access	40.24	0.0	1	1	100.00
		flash_ctrl_stress_all	397.79	0.0	1	1	100.00
		flash_ctrl_connect	9.89	0.0	1	1	100.00
		flash_ctrl_rd_intg	15.54	0.0	1	1	100.00
		flash_ctrl_wr_intg	6.75	0.0	1	1	100.00
		flash_ctrl_access_after_disable	5.91	0.0	1	1	100.00
		flash_ctrl_fs_sup	22.28	0.0	1	1	100.00
		flash_ctrl_phy_arb_redun	9.39	0.0	1	1	100.00
		flash_ctrl_phy_host_grant_err	7.67	0.0	1	1	100.00
		flash_ctrl_phy_ack_consistency	7.13	0.0	1	1	100.00
		flash_ctrl_config_regwen	6.92	0.0	1	1	100.00
		flash_ctrl_rma_err	724.9	0.0	1	1	100.00
		flash_ctrl_lcmgr_intg	5.64	0.0	1	1	100.00
		flash_ctrl_hw_read_seed_err	8.64	0.0	1	1	100.00
		flash_ctrl_hw_prog_rma_wipe_err	59.15	0.0	1	1	100.00
		flash_ctrl_rd_ooo	22.94	0.0	1	1	100.00
		flash_ctrl_host_addr_infection	13.9	0.0	1	1	100.00
		flash_ctrl_basic_rw	299.73	0.0	1	1	100.00
		flash_ctrl_alert_test	6.0	0.0	1	1	100.00
		flash_ctrl_tl_errors	7.48	0.0	1	1	100.00
		flash_ctrl_tl_intg_err	178.33	0.0	1	1	100.00
		flash_ctrl_shadow_reg_errors	12.97	0.0	1	1	100.00
		flash_ctrl_shadow_reg_errors_with_csr_rw	24.93	0.0	1	1	100.00
		flash_ctrl_intr_test	6.88	0.0	1	1	100.00
		flash_ctrl_mem_walk	6.39	0.0	1	1	100.00
		flash_ctrl_mem_partial_access	5.72	0.0	1	1	100.00
		flash_ctrl_csr_hw_reset	10.06	0.0	1	1	100.00
		flash_ctrl_csr_rw	7.14	0.0	1	1	100.00
		flash_ctrl_csr_bit_bash	30.69	0.0	1	1	100.00
		flash_ctrl_csr_aliasing	33.9	0.0	1	1	100.00
		flash_ctrl_same_csr_outstanding	15.87	0.0	1	1	100.00
		flash_ctrl_csr_mem_rw_with_rand_reset	8.43	0.0	1	1	100.00
		prim_esc_test	0.65	0.0	1	1	100.00
		rstmgr_cnsty_chk_test	2.49	0.0	1	1	100.00
		rv_timer_tl_errors	1.93	0.0	1	1	100.00
		rv_timer_tl_intg_err	1.46	0.0	1	1	100.00
		rv_timer_intr_test	0.73	0.0	1	1	100.00
		rv_timer_csr_hw_reset	0.62	0.0	1	1	100.00
		rv_timer_csr_rw	0.58	0.0	1	1	100.00
		rv_timer_csr_bit_bash	2.76	0.0	1	1	100.00
		rv_timer_csr_aliasing	0.65	0.0	1	1	100.00
		rv_timer_same_csr_outstanding	0.75	0.0	1	1	100.00
		rv_timer_csr_mem_rw_with_rand_reset	0.7	0.0	1	1	100.00
		rv_timer_random	0.9	0.0	1	1	100.00
		rv_timer_min	0.74	0.0	1	1	100.00
		rv_timer_max	0.66	0.0	0	1	0.00
		rv_timer_disabled	0.67	0.0	1	1	100.00
		rv_timer_cfg_update_on_fly	0.68	0.0	1	1	100.00
		rv_timer_random_reset	0.62	0.0	0	1	0.00
		rv_timer_stress_all_with_rand_reset	10.11	0.0	1	1	100.00
		rv_timer_stress_all	3.15	0.0	1	1	100.00
		rv_timer_sec_cm	0.74	0.0	1	1	100.00
		rv_timer_alert_test	0.52	0.0	1	1	100.00
		pwrmgr_tl_errors	1.12	0.0	1	1	100.00
		pwrmgr_tl_intg_err	0.66	0.0	0	1	0.00
		pwrmgr_intr_test	0.74	0.0	1	1	100.00
		pwrmgr_csr_hw_reset	0.71	0.0	1	1	100.00
		pwrmgr_csr_rw	0.66	0.0	1	1	100.00
		pwrmgr_csr_bit_bash	2.12	0.0	1	1	100.00
		pwrmgr_csr_aliasing	1.01	0.0	1	1	100.00
		pwrmgr_same_csr_outstanding	0.73	0.0	1	1	100.00
		pwrmgr_csr_mem_rw_with_rand_reset	0.76	0.0	1	1	100.00
		pwrmgr_smoke	0.76	0.0	1	1	100.00
		pwrmgr_reset	0.77	0.0	1	1	100.00
		pwrmgr_lowpower_wakeup_race	0.93	0.0	1	1	100.00
		pwrmgr_wakeup	0.79	0.0	1	1	100.00
		pwrmgr_wakeup_reset	0.76	0.0	1	1	100.00
		pwrmgr_aborted_low_power	0.74	0.0	1	1	100.00
		pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.63	0.0	1	1	100.00
		pwrmgr_sec_cm_rstmgr_intersig_mubi	0.81	0.0	1	1	100.00
		pwrmgr_esc_clk_rst_malfunc	0.65	0.0	1	1	100.00
		pwrmgr_sec_cm_ctrl_config_regwen	0.91	0.0	1	1	100.00
		pwrmgr_global_esc	0.63	0.0	1	1	100.00
		pwrmgr_escalation_timeout	0.72	0.0	0	1	0.00
		pwrmgr_glitch	0.6	0.0	1	1	100.00
		pwrmgr_disable_rom_integrity_check	0.63	0.0	1	1	100.00
		pwrmgr_reset_invalid	0.79	0.0	1	1	100.00
		pwrmgr_lowpower_invalid	0.67	0.0	1	1	100.00
		pwrmgr_sec_cm	0.79	0.0	0	1	0.00
		pwrmgr_stress_all_with_rand_reset	8.57	0.0	1	1	100.00
		pwrmgr_stress_all	0.64	0.0	1	1	100.00
		rv_dm_csr_aliasing	51.85	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_hw_reset	0.73	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_rw	1.25	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_bit_bash	3.66	0.0	1	1	100.00
		rv_dm_jtag_dtm_csr_aliasing	0.86	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_hw_reset	5.15	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_rw	4.99	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_bit_bash	4.2	0.0	1	1	100.00
		rv_dm_jtag_dmi_csr_aliasing	74.06	0.0	1	1	100.00
		rv_dm_tap_fsm_rand_reset	0.83	0.0	0	1	0.00
		rv_dm_tl_errors	2.45	0.0	0	1	0.00
		rv_dm_tl_intg_err	8.75	0.0	1	1	100.00
		rv_dm_mem_walk	0.73	0.0	1	1	100.00
		rv_dm_mem_partial_access	0.71	0.0	1	1	100.00
		rv_dm_csr_hw_reset	1.79	0.0	1	1	100.00
		rv_dm_csr_rw	1.3	0.0	1	1	100.00
		rv_dm_csr_bit_bash	38.34	0.0	1	1	100.00
		rv_dm_same_csr_outstanding	3.49	0.0	1	1	100.00
		rv_dm_csr_mem_rw_with_rand_reset	0.78	0.0	0	1	0.00
		rv_dm_smoke	1.19	0.0	1	1	100.00
		rv_dm_tap_fsm	9.7	0.0	1	1	100.00
		rv_dm_sba_tl_access	145.86	0.0	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	545.95	0.0	0	1	0.00
		rv_dm_bad_sba_tl_access	73.09	0.0	0	1	0.00
		rv_dm_autoincr_sba_tl_access	107.61	0.0	0	1	0.00
		rv_dm_cmderr_busy	1.45	0.0	1	1	100.00
		rv_dm_cmderr_not_supported	0.92	0.0	1	1	100.00
		rv_dm_cmderr_exception	1.32	0.0	1	1	100.00
		rv_dm_mem_tl_access_halted	0.78	0.0	1	1	100.00
		rv_dm_mem_tl_access_resuming	0.91	0.0	1	1	100.00
		rv_dm_hart_unavail	0.96	0.0	1	1	100.00
		rv_dm_cmderr_halt_resume	1.17	0.0	1	1	100.00
		rv_dm_dataaddr_rw_access	0.76	0.0	1	1	100.00
		rv_dm_halt_resume_whereto	2.1	0.0	1	1	100.00
		rv_dm_sba_debug_disabled	2.22	0.0	1	1	100.00
		rv_dm_ndmreset_req	1.08	0.0	1	1	100.00
		rv_dm_jtag_dtm_idle_hint	1.37	0.0	1	1	100.00
		rv_dm_jtag_dmi_dm_inactive	2.01	0.0	1	1	100.00
		rv_dm_jtag_dmi_debug_disabled	0.85	0.0	1	1	100.00
		rv_dm_jtag_dtm_hard_reset	2.43	0.0	1	1	100.00
		rv_dm_abstractcmd_status	0.88	0.0	1	1	100.00
		rv_dm_rom_read_access	1.07	0.0	1	1	100.00
		rv_dm_progbuf_read_write_execute	1.22	0.0	1	1	100.00
		rv_dm_debug_disabled	1.03	0.0	1	1	100.00
		rv_dm_dmi_failed_op	1.23	0.0	1	1	100.00
		rv_dm_hartsel_warl	0.86	0.0	1	1	100.00
		rv_dm_buffered_enable	1.21	0.0	1	1	100.00
		rv_dm_sparse_lc_gate_fsm	0.87	0.0	1	1	100.00
		rv_dm_scanmode	0.67	0.0	1	1	100.00
		rv_dm_stress_all	2.09	0.0	1	1	100.00
		rv_dm_stress_all_with_rand_reset	0.66	0.0	0	1	0.00
		rv_dm_sec_cm	1.76	0.0	1	1	100.00
		rv_dm_alert_test	0.71	0.0	1	1	100.00
		edn_tl_errors	2.03	0.0	1	1	100.00
		edn_tl_intg_err	4.45	0.0	1	1	100.00
		edn_intr_test	0.96	0.0	1	1	100.00
		edn_csr_hw_reset	0.77	0.0	1	1	100.00
		edn_csr_rw	0.83	0.0	1	1	100.00
		edn_csr_bit_bash	2.44	0.0	1	1	100.00
		edn_csr_aliasing	1.39	0.0	1	1	100.00
		edn_same_csr_outstanding	0.97	0.0	1	1	100.00
		edn_csr_mem_rw_with_rand_reset	1.03	0.0	1	1	100.00
		edn_smoke	0.93	0.0	1	1	100.00
		edn_regwen	1.09	0.0	1	1	100.00
		edn_genbits	1.17	0.0	1	1	100.00
		edn_stress_all	1.12	0.0	1	1	100.00
		edn_stress_all_with_rand_reset	0.0	0.0	0	1	0.00
		edn_intr	0.98	0.0	1	1	100.00
		edn_alert	1.43	0.0	1	1	100.00
		edn_err	1.07	0.0	1	1	100.00
		edn_disable	0.83	0.0	1	1	100.00
		edn_disable_auto_req_mode	1.12	0.0	1	1	100.00
		edn_sec_cm	4.22	0.0	1	1	100.00
		edn_alert_test	0.85	0.0	1	1	100.00
		aon_timer_smoke	1.29	0.0	1	1	100.00
		aon_timer_prescaler	19.79	0.0	1	1	100.00
		aon_timer_jump	1.1	0.0	1	1	100.00
		aon_timer_custom_intr	1.11	0.0	1	1	100.00
		aon_timer_smoke_max_thold	1.49	0.0	1	1	100.00
		aon_timer_smoke_min_thold	0.93	0.0	1	1	100.00
		aon_timer_wkup_count_cdc_hi	5.79	0.0	1	1	100.00
		aon_timer_alternating_enable_on_off	11.25	0.0	1	1	100.00
		aon_timer_stress_all_with_rand_reset	8.66	0.0	1	1	100.00
		aon_timer_stress_all	59.03	0.0	1	1	100.00
		aon_timer_sec_cm	2.97	0.0	1	1	100.00
		aon_timer_alert_test	1.0	0.0	1	1	100.00
		aon_timer_tl_errors	1.94	0.0	1	1	100.00
		aon_timer_tl_intg_err	2.55	0.0	1	1	100.00
		aon_timer_intr_test	1.27	0.0	1	1	100.00
		aon_timer_mem_walk	0.87	0.0	1	1	100.00
		aon_timer_mem_partial_access	0.89	0.0	1	1	100.00
		aon_timer_csr_hw_reset	0.82	0.0	1	1	100.00
		aon_timer_csr_rw	0.88	0.0	1	1	100.00
		aon_timer_csr_bit_bash	1.51	0.0	1	1	100.00
		aon_timer_csr_aliasing	0.95	0.0	1	1	100.00
		aon_timer_same_csr_outstanding	4.57	0.0	1	1	100.00
		aon_timer_csr_mem_rw_with_rand_reset	0.87	0.0	1	1	100.00
		usbdev_tl_errors	1.55	0.0	1	1	100.00
		usbdev_tl_intg_err	3.49	0.0	1	1	100.00
		usbdev_intr_test	0.77	0.0	1	1	100.00
		usbdev_mem_walk	3.86	0.0	1	1	100.00
		usbdev_mem_partial_access	1.18	0.0	1	1	100.00
		usbdev_csr_hw_reset	1.14	0.0	1	1	100.00
		usbdev_csr_rw	1.03	0.0	1	1	100.00
		usbdev_csr_bit_bash	3.67	0.0	1	1	100.00
		usbdev_csr_aliasing	1.56	0.0	1	1	100.00
		usbdev_same_csr_outstanding	1.37	0.0	1	1	100.00
		usbdev_csr_mem_rw_with_rand_reset	1.27	0.0	1	1	100.00
		kmac_shadow_reg_errors	1.84	0.0	2	2	100.00
		kmac_shadow_reg_errors_with_csr_rw	4.14	0.0	2	2	100.00
		kmac_mem_walk	0.84	0.0	2	2	100.00
		kmac_mem_partial_access	1.31	0.0	2	2	100.00
		kmac_tl_errors	2.13	0.0	2	2	100.00
		kmac_tl_intg_err	3.56	0.0	2	2	100.00
		kmac_intr_test	0.91	0.0	2	2	100.00
		kmac_csr_hw_reset	1.32	0.0	2	2	100.00
		kmac_csr_rw	1.0	0.0	2	2	100.00
		kmac_csr_bit_bash	5.96	0.0	2	2	100.00
		kmac_csr_aliasing	6.97	0.0	2	2	100.00
		kmac_same_csr_outstanding	1.88	0.0	2	2	100.00
		kmac_csr_mem_rw_with_rand_reset	1.82	0.0	2	2	100.00
		usbdev_aon_wake_disconnect	5.64	0.0	1	1	100.00
		usbdev_aon_wake_reset	14.18	0.0	1	1	100.00
		usbdev_aon_wake_resume	29.83	0.0	1	1	100.00
		usbdev_av_buffer	0.85	0.0	1	1	100.00
		usbdev_av_empty	0.92	0.0	1	1	100.00
		usbdev_av_overflow	0.76	0.0	1	1	100.00
		usbdev_bitstuff_err	0.78	0.0	1	1	100.00
		usbdev_data_toggle_clear	1.27	0.0	1	1	100.00
		usbdev_data_toggle_restore	1.3	0.0	1	1	100.00
		usbdev_device_address	52.01	0.0	1	1	100.00
		usbdev_device_timeout	3.67	0.0	1	1	100.00
		usbdev_timeout_missing_host_handshake	10.71	0.0	1	1	100.00
		usbdev_disable_endpoint	1.4	0.0	1	1	100.00
		usbdev_disconnected	1.18	0.0	1	1	100.00
		usbdev_dpi_config_host	96.96	0.0	1	1	100.00
		usbdev_enable	0.89	0.0	1	1	100.00
		usbdev_endpoint_access	1.73	0.0	1	1	100.00
		usbdev_endpoint_types	0.84	0.0	1	1	100.00
		usbdev_fifo_levels	0.98	0.0	1	1	100.00
		usbdev_fifo_rst	1.87	0.0	1	1	100.00
		usbdev_freq_hiclk	114.73	0.0	1	1	100.00
		usbdev_freq_hiclk_max	119.46	0.0	1	1	100.00
		usbdev_freq_loclk	147.12	0.0	1	1	100.00
		usbdev_freq_loclk_max	125.1	0.0	1	1	100.00
		usbdev_freq_phase	120.05999999999999	0.0	1	1	100.00
		usbdev_host_lost	6.85	0.0	1	1	100.00
		usbdev_invalid_data1_data0_toggle_test	1.84	0.0	1	1	100.00
		usbdev_invalid_sync	44.61	0.0	1	1	100.00
		usbdev_in_iso	1.15	0.0	1	1	100.00
		usbdev_in_stall	1.21	0.0	1	1	100.00
		usbdev_in_trans	1.45	0.0	1	1	100.00
		usbdev_iso_retraction	99.01	0.0	1	1	100.00
		usbdev_link_in_err	1.38	0.0	1	1	100.00
		usbdev_link_out_err	1.34	0.0	1	1	100.00
		usbdev_link_reset	1.01	0.0	1	1	100.00
		usbdev_link_resume	33.54	0.0	1	1	100.00
		usbdev_link_suspend	6.29	0.0	1	1	100.00
		usbdev_low_speed_traffic	52.22	0.0	1	1	100.00
		usbdev_max_inter_pkt_delay	22.37	0.0	1	1	100.00
		usbdev_max_length_in_transaction	1.42	0.0	1	1	100.00
		usbdev_max_length_out_transaction	1.48	0.0	1	1	100.00
		usbdev_max_non_iso_usb_traffic	17.18	0.0	1	1	100.00
		usbdev_max_usb_traffic	12.18	0.0	1	1	100.00
		usbdev_min_inter_pkt_delay	13.23	0.0	1	1	100.00
		usbdev_min_length_in_transaction	1.17	0.0	1	1	100.00
		usbdev_min_length_out_transaction	1.19	0.0	1	1	100.00
		usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full	2.1	0.0	1	1	100.00
		usbdev_nak_trans	1.31	0.0	1	1	100.00
		usbdev_out_iso	0.89	0.0	1	1	100.00
		usbdev_out_stall	1.04	0.0	1	1	100.00
		usbdev_out_trans_nak	1.2	0.0	1	1	100.00
		usbdev_pending_in_trans	1.02	0.0	1	1	100.00
		usbdev_phy_config_eop_single_bit_handling	0.89	0.0	1	1	100.00
		usbdev_phy_config_pinflip	1.05	0.0	1	1	100.00
		usbdev_phy_config_rand_bus_type	1.01	0.0	1	1	100.00
		usbdev_phy_config_rx_dp_dn	1.0	0.0	1	1	100.00
		usbdev_phy_config_tx_osc_test_mode	1.2	0.0	1	1	100.00
		usbdev_phy_config_tx_use_d_se0	0.91	0.0	1	1	100.00
		usbdev_phy_config_usb_ref_disable	0.94	0.0	1	1	100.00
		usbdev_phy_pins_sense	0.87	0.0	1	1	100.00
		usbdev_pkt_buffer	11.24	0.0	1	1	100.00
		usbdev_pkt_received	0.88	0.0	1	1	100.00
		usbdev_pkt_sent	1.04	0.0	1	1	100.00
		usbdev_random_length_in_transaction	1.06	0.0	1	1	100.00
		usbdev_random_length_out_transaction	1.02	0.0	1	1	100.00
		usbdev_rand_bus_disconnects	42.07	0.0	1	1	100.00
		usbdev_rand_bus_resets	136.49	0.0	1	1	100.00
		usbdev_rand_suspends	72.06	0.0	1	1	100.00
		usbdev_resume_link_active	14.82	0.0	1	1	100.00
		usbdev_rxenable_out	0.92	0.0	1	1	100.00
		usbdev_rx_crc_err	0.93	0.0	1	1	100.00
		usbdev_rx_full	1.2	0.0	1	1	100.00
		usbdev_rx_pid_err	1.11	0.0	1	1	100.00
		usbdev_setup_priority	1.19	0.0	1	1	100.00
		usbdev_setup_priority_over_stall_response	1.13	0.0	1	1	100.00
		usbdev_setup_stage	1.08	0.0	1	1	100.00
		usbdev_setup_trans_ignored	0.89	0.0	1	1	100.00
		usbdev_smoke	0.9	0.0	1	1	100.00
		usbdev_spurious_pids_ignored	28.53	0.0	1	1	100.00
		usbdev_stall_priority_over_nak	0.94	0.0	1	1	100.00
		usbdev_stall_trans	0.76	0.0	1	1	100.00
		usbdev_streaming_out	25.1	0.0	1	1	100.00
		usbdev_stream_len_max	2.79	0.0	1	1	100.00
		usbdev_stress_all_with_rand_reset	0.62	0.0	0	1	0.00
		usbdev_stress_usb_traffic	99.9	0.0	1	1	100.00
		usbdev_tx_rx_disruption	1.93	0.0	1	1	100.00
		usbdev_stress_all	0.81	0.0	0	1	0.00
		usbdev_sec_cm	1.57	0.0	1	1	100.00
		usbdev_alert_test	0.74	0.0	1	1	100.00
		lc_ctrl_jtag_csr_hw_reset	2.77	0.0	2	2	100.00
		lc_ctrl_jtag_csr_rw	1.45	0.0	2	2	100.00
		lc_ctrl_jtag_csr_bit_bash	9.6	0.0	2	2	100.00
		lc_ctrl_jtag_csr_aliasing	5.11	0.0	2	2	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.56	0.0	2	2	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.47	0.0	2	2	100.00
		lc_ctrl_jtag_alert_test	1.87	0.0	2	2	100.00
		lc_ctrl_tl_errors	1.47	0.0	2	2	100.00
		lc_ctrl_tl_intg_err	2.56	0.0	2	2	100.00
		lc_ctrl_csr_hw_reset	1.07	0.0	2	2	100.00
		lc_ctrl_csr_rw	1.0	0.0	2	2	100.00
		lc_ctrl_csr_bit_bash	1.39	0.0	2	2	100.00
		lc_ctrl_csr_aliasing	1.25	0.0	2	2	100.00
		lc_ctrl_same_csr_outstanding	1.31	0.0	2	2	100.00
		lc_ctrl_csr_mem_rw_with_rand_reset	1.07	0.0	2	2	100.00
		lc_ctrl_smoke	2.15	0.0	2	2	100.00
		lc_ctrl_volatile_unlock_smoke	1.16	0.0	2	2	100.00
		lc_ctrl_state_failure	7.95	0.0	0	2	0.00
		lc_ctrl_state_post_trans	3.61	0.0	0	2	0.00
		lc_ctrl_prog_failure	2.66	0.0	2	2	100.00
		lc_ctrl_errors	8.18	0.0	2	2	100.00
		lc_ctrl_security_escalation	7.67	0.0	2	2	100.00
		lc_ctrl_regwen_during_op	9.39	0.0	2	2	100.00
		lc_ctrl_claim_transition_if	1.07	0.0	2	2	100.00
		lc_ctrl_jtag_smoke	5.5	0.0	2	2	100.00
		lc_ctrl_jtag_state_failure	2.22	0.0	0	2	0.00
		lc_ctrl_jtag_state_post_trans	4.65	0.0	0	2	0.00
		lc_ctrl_jtag_prog_failure	7.1	0.0	2	2	100.00
		lc_ctrl_jtag_errors	34.85	0.0	2	2	100.00
		lc_ctrl_jtag_access	6.69	0.0	2	2	100.00
		lc_ctrl_jtag_priority	4.08	0.0	2	2	100.00
		lc_ctrl_jtag_regwen_during_op	24.51	0.0	2	2	100.00
		lc_ctrl_sec_mubi	5.11	0.0	2	2	100.00
		lc_ctrl_sec_token_mux	6.88	0.0	2	2	100.00
		lc_ctrl_sec_token_digest	4.79	0.0	2	2	100.00
		lc_ctrl_stress_all	109.96	0.0	1	2	50.00
		lc_ctrl_stress_all_with_rand_reset	49.7	0.0	0	2	0.00
		lc_ctrl_sec_cm	7.15	0.0	2	2	100.00
		lc_ctrl_alert_test	1.15	0.0	2	2	100.00
		kmac_smoke	32.53	0.0	2	2	100.00
		kmac_long_msg_and_output	2071.68	0.0	2	2	100.00
		kmac_sideload	291.18	0.0	2	2	100.00
		kmac_sideload_invalid	87.39	0.0	1	2	50.00
		kmac_burst_write	966.7	0.0	2	2	100.00
		kmac_test_vectors_sha3_224	1548.54	0.0	2	2	100.00
		kmac_test_vectors_sha3_256	28.97	0.0	2	2	100.00
		kmac_test_vectors_sha3_384	1242.57	0.0	2	2	100.00
		kmac_test_vectors_sha3_512	854.83	0.0	2	2	100.00
		kmac_test_vectors_shake_128	1480.98	0.0	2	2	100.00
		kmac_test_vectors_shake_256	263.39	0.0	2	2	100.00
		kmac_test_vectors_kmac	3.24	0.0	2	2	100.00
		kmac_test_vectors_kmac_xof	3.21	0.0	2	2	100.00
		kmac_app	125.88	0.0	2	2	100.00
		kmac_app_with_partial_data	218.78	0.0	2	2	100.00
		kmac_entropy_refresh	251.54999999999998	0.0	2	2	100.00
		kmac_mubi	80.03	0.0	2	2	100.00
		kmac_error	241.15000000000003	0.0	2	2	100.00
		kmac_key_error	8.01	0.0	2	2	100.00
		kmac_edn_timeout_error	23.29	0.0	2	2	100.00
		kmac_entropy_mode_error	8.15	0.0	2	2	100.00
		kmac_entropy_ready_error	64.5	0.0	2	2	100.00
		kmac_lc_escalation	1.65	0.0	2	2	100.00
		kmac_stress_all	891.11	0.0	2	2	100.00
		kmac_stress_all_with_rand_reset	77.86	0.0	2	2	100.00
		kmac_sec_cm	47.1	0.0	2	2	100.00
		kmac_alert_test	1.07	0.0	2	2	100.00
		pattgen_smoke	13.0	604.1847369999999	1	1	100.00
		pattgen_perf	186.0	53134.001588	1	1	100.00
		pattgen_error	11.0	37.002922	1	1	100.00
		cnt_rollover	16.0	952.029776	1	1	100.00
		pattgen_inactive_level	44.0	10114.187068	0	1	0.00
		pattgen_sec_cm	5.0	248.54200899999998	1	1	100.00
		pattgen_stress_all_with_rand_reset	31.0	3984.128891	0	1	0.00
		pattgen_stress_all	7761.0	10000000.0	0	1	0.00
		pattgen_alert_test	2.0	32.184151	1	1	100.00
		pattgen_tl_errors	2.0	63.221494	1	1	100.00
		pattgen_tl_intg_err	1.0	367.788809	1	1	100.00
		pattgen_intr_test	1.0	14.241837	1	1	100.00
		pattgen_csr_hw_reset	1.0	37.838072999999994	1	1	100.00
		pattgen_csr_rw	2.0	13.96878	1	1	100.00
		pattgen_csr_bit_bash	2.0	592.06205	1	1	100.00
		pattgen_csr_aliasing	1.0	172.305757	1	1	100.00
		pattgen_same_csr_outstanding	1.0	84.037235	1	1	100.00
		pattgen_csr_mem_rw_with_rand_reset	1.0	16.548441	1	1	100.00
		spi_host_smoke	21.0	1097.064731	1	1	100.00
		spi_host_speed	4.0	73.409951	1	1	100.00
		spi_host_upper_range_clkdiv	200.0	5755.774898	1	1	100.00
		spi_host_performance	2.0	25.752883999999998	1	1	100.00
		spi_host_sw_reset	37.0	2416.540014	1	1	100.00
		spi_host_overflow_underflow	2.0	45.68642	1	1	100.00
		spi_host_error_cmd	1.0	45.592046	1	1	100.00
		spi_host_event	17.0	626.29673	1	1	100.00
		spi_host_passthrough_mode	1.0	62.38257	1	1	100.00
		spi_host_status_stall	69.0	2263.036067	1	1	100.00
		spi_host_idlecsbactive	3.0	224.339036	1	1	100.00
		spi_host_stress_all	4.0	404.962539	1	1	100.00
		spi_host_spien	4.0	380.37473	1	1	100.00
		spi_host_sec_cm	2.0	71.95317200000001	1	1	100.00
		spi_host_alert_test	2.0	15.95419	1	1	100.00
		spi_host_tl_errors	2.0	113.34584600000001	1	1	100.00
		spi_host_tl_intg_err	2.0	103.19741400000001	1	1	100.00
		spi_host_intr_test	1.0	20.106552	1	1	100.00
		spi_host_mem_walk	1.0	45.468044	1	1	100.00
		spi_host_mem_partial_access	1.0	45.661873	1	1	100.00
		spi_host_csr_hw_reset	1.0	29.037446	1	1	100.00
		spi_host_csr_rw	1.0	56.280308	1	1	100.00
		spi_host_csr_bit_bash	3.0	116.013141	1	1	100.00
		spi_host_csr_aliasing	1.0	23.088988	1	1	100.00
		spi_host_same_csr_outstanding	2.0	22.647348	1	1	100.00
		spi_host_csr_mem_rw_with_rand_reset	2.0	38.178115	1	1	100.00
		pwm_smoke	3.0	542.5186	1	1	100.00
		pwm_rand_output	37.0	52490.60423	1	1	100.00
		pwm_heartbeat_wrap	40.0	41996.551501	1	1	100.00
		pwm_perf	31.0	38891.665908	1	1	100.00
		pwm_phase	33.0	10508.741069	1	1	100.00
		pwm_regwen	148.0	42011.934782	1	1	100.00
		pwm_stress_all	84.0	36289.326983000006	1	1	100.00
		pwm_sec_cm	2.0	129.37153	1	1	100.00
		pwm_alert_test	1.0	24.009867999999997	1	1	100.00
		pwm_tl_errors	3.0	96.29767	1	1	100.00
		pwm_tl_intg_err	3.0	357.672822	1	1	100.00
		pwm_csr_hw_reset	2.0	84.15135000000001	1	1	100.00
		pwm_csr_rw	1.0	20.259446	1	1	100.00
		pwm_csr_bit_bash	5.0	1681.7715130000001	1	1	100.00
		pwm_csr_aliasing	2.0	80.368427	1	1	100.00
		pwm_same_csr_outstanding	2.0	33.16672	1	1	100.00
		pwm_csr_mem_rw_with_rand_reset	2.0	36.460601000000004	1	1	100.00
		sram_ctrl_passthru_mem_tl_intg_err	29.89	0.0	2	2	100.00
		sram_ctrl_tl_errors	3.09	0.0	2	2	100.00
		sram_ctrl_tl_intg_err	1.43	0.0	2	2	100.00
		sram_ctrl_csr_hw_reset	0.81	0.0	2	2	100.00
		sram_ctrl_csr_rw	0.75	0.0	2	2	100.00
		sram_ctrl_csr_bit_bash	1.94	0.0	2	2	100.00
		sram_ctrl_csr_aliasing	1.03	0.0	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.93	0.0	2	2	100.00
		sram_ctrl_csr_mem_rw_with_rand_reset	2.72	0.0	2	2	100.00
		sram_ctrl_smoke	19.99	0.0	2	2	100.00
		sram_ctrl_multiple_keys	503.17999999999995	0.0	2	2	100.00
		sram_ctrl_bijection	1316.91	0.0	2	2	100.00
		sram_ctrl_stress_pipeline	149.95	0.0	2	2	100.00
		sram_ctrl_partial_access	61.849999999999994	0.0	2	2	100.00
		sram_ctrl_partial_access_b2b	358.33	0.0	2	2	100.00
		sram_ctrl_max_throughput	53.98	0.0	2	2	100.00
		sram_ctrl_throughput_w_partial_write	31.32	0.0	2	2	100.00
		sram_ctrl_throughput_w_readback	37.33	0.0	2	2	100.00
		sram_ctrl_lc_escalation	56.16	0.0	2	2	100.00
		sram_ctrl_access_during_key_req	640.27	0.0	2	2	100.00
		sram_ctrl_executable	886.23	0.0	2	2	100.00
		sram_ctrl_regwen	286.16	0.0	2	2	100.00
		sram_ctrl_ram_cfg	3.39	0.0	2	2	100.00
		sram_ctrl_mem_walk	233.76	0.0	2	2	100.00
		sram_ctrl_mem_partial_access	47.3	0.0	2	2	100.00
		sram_ctrl_readback_err	7.12	0.0	1	2	50.00
		sram_ctrl_mubi_enc_err	3.92	0.0	1	2	50.00
		sram_ctrl_stress_all_with_rand_reset	32.56	0.0	2	2	100.00
		sram_ctrl_stress_all	5042.3	0.0	2	2	100.00
		sram_ctrl_sec_cm	0.81	0.0	0	2	0.00
		sram_ctrl_alert_test	0.96	0.0	2	2	100.00
		rom_ctrl_smoke	7.95	0.0	2	2	100.00
		rom_ctrl_stress_all	30.0	0.0	2	2	100.00
		rom_ctrl_max_throughput_chk	10.74	0.0	2	2	100.00
		rom_ctrl_corrupt_sig_fatal_chk	85.95	0.0	2	2	100.00
		rom_ctrl_kmac_err_chk	14.25	0.0	2	2	100.00
		rom_ctrl_stress_all_with_rand_reset	77.25	0.0	2	2	100.00
		rom_ctrl_sec_cm	231.93	0.0	0	2	0.00
		rom_ctrl_alert_test	8.13	0.0	2	2	100.00
		rom_ctrl_passthru_mem_tl_intg_err	40.88	0.0	2	2	100.00
		rom_ctrl_tl_errors	8.47	0.0	2	2	100.00
		rom_ctrl_tl_intg_err	50.56	0.0	2	2	100.00
		rom_ctrl_mem_walk	5.87	0.0	2	2	100.00
		rom_ctrl_mem_partial_access	9.1	0.0	2	2	100.00
		rom_ctrl_csr_hw_reset	9.59	0.0	2	2	100.00
		rom_ctrl_csr_rw	6.55	0.0	2	2	100.00
		rom_ctrl_csr_bit_bash	7.71	0.0	2	2	100.00
		rom_ctrl_csr_aliasing	6.89	0.0	2	2	100.00
		rom_ctrl_same_csr_outstanding	6.38	0.0	2	2	100.00
		rom_ctrl_csr_mem_rw_with_rand_reset	6.72	0.0	2	2	100.00
		alert_handler_smoke	39.49	0.0	1	1	100.00
		alert_handler_random_alerts	10.12	0.0	1	1	100.00
		alert_handler_random_classes	27.4	0.0	1	1	100.00
		alert_handler_esc_intr_timeout	31.3	0.0	1	1	100.00
		alert_handler_esc_alert_accum	212.89	0.0	1	1	100.00
		alert_handler_sig_int_fail	31.75	0.0	1	1	100.00
		alert_handler_entropy	466.19	0.0	1	1	100.00
		alert_handler_ping_timeout	13.2	0.0	0	1	0.00
		alert_handler_lpg	1527.12	0.0	1	1	100.00
		alert_handler_lpg_stub_clk	1731.15	0.0	1	1	100.00
		alert_handler_entropy_stress	28.05	0.0	1	1	100.00
		alert_handler_stress_all	2130.19	0.0	1	1	100.00
		alert_handler_alert_accum_saturation	2.92	0.0	1	1	100.00
		alert_handler_stress_all_with_rand_reset	273.53	0.0	1	1	100.00
		alert_handler_sec_cm	9.12	0.0	1	1	100.00
		alert_handler_shadow_reg_errors_with_csr_rw	329.72	0.0	1	1	100.00
		alert_handler_shadow_reg_errors	198.42	0.0	1	1	100.00
		alert_handler_tl_errors	7.26	0.0	1	1	100.00
		alert_handler_tl_intg_err	29.94	0.0	1	1	100.00
		alert_handler_intr_test	2.01	0.0	1	1	100.00
		alert_handler_csr_hw_reset	4.3	0.0	1	1	100.00
		alert_handler_csr_rw	2.61	0.0	1	1	100.00
		alert_handler_csr_bit_bash	134.37	0.0	1	1	100.00
		alert_handler_csr_aliasing	44.64	0.0	1	1	100.00
		alert_handler_same_csr_outstanding	17.94	0.0	1	1	100.00
		alert_handler_csr_mem_rw_with_rand_reset	3.81	0.0	1	1	100.00
		otp_ctrl_tl_errors	5.72	0.0	1	1	100.00
		otp_ctrl_tl_intg_err	7.95	0.0	1	1	100.00
		otp_ctrl_intr_test	1.95	0.0	1	1	100.00
		otp_ctrl_mem_walk	2.07	0.0	1	1	100.00
		otp_ctrl_mem_partial_access	1.97	0.0	1	1	100.00
		otp_ctrl_csr_hw_reset	3.4	0.0	1	1	100.00
		otp_ctrl_csr_rw	2.16	0.0	1	1	100.00
		otp_ctrl_csr_bit_bash	6.83	0.0	1	1	100.00
		otp_ctrl_csr_aliasing	2.69	0.0	1	1	100.00
		otp_ctrl_same_csr_outstanding	2.76	0.0	1	1	100.00
		otp_ctrl_csr_mem_rw_with_rand_reset	2.42	0.0	1	1	100.00
		otp_ctrl_wake_up	1.53	0.0	1	1	100.00
		otp_ctrl_smoke	4.83	0.0	1	1	100.00
		otp_ctrl_partition_walk	14.49	0.0	1	1	100.00
		otp_ctrl_low_freq_read	10.11	0.0	1	1	100.00
		otp_ctrl_init_fail	2.84	0.0	1	1	100.00
		otp_ctrl_background_chks	25.61	0.0	1	1	100.00
		otp_ctrl_parallel_lc_req	14.43	0.0	1	1	100.00
		otp_ctrl_parallel_lc_esc	3.09	0.0	1	1	100.00
		otp_ctrl_dai_lock	21.34	0.0	1	1	100.00
		otp_ctrl_dai_errs	2.84	0.0	0	1	0.00
		otp_ctrl_check_fail	5.29	0.0	0	1	0.00
		otp_ctrl_macro_errs	3.99	0.0	1	1	100.00
		otp_ctrl_parallel_key_req	8.19	0.0	1	1	100.00
		otp_ctrl_regwen	11.4	0.0	1	1	100.00
		otp_ctrl_test_access	19.4	0.0	1	1	100.00
		otp_ctrl_stress_all_with_rand_reset	1.97	0.0	0	1	0.00
		otp_ctrl_stress_all	92.24	0.0	1	1	100.00
		otp_ctrl_sec_cm	104.6	0.0	1	1	100.00
		otp_ctrl_alert_test	1.44	0.0	1	1	100.00
		aes_tl_errors	3.0	83.522987	2	2	100.00
		aes_tl_intg_err	3.0	514.2162089999999	2	2	100.00
		aes_shadow_reg_errors	3.0	98.132893	2	2	100.00
		aes_shadow_reg_errors_with_csr_rw	3.0	529.061796	2	2	100.00
		aes_csr_hw_reset	2.0	172.311705	2	2	100.00
		aes_csr_rw	2.0	110.511208	2	2	100.00
		aes_csr_bit_bash	6.0	1626.6806259999998	2	2	100.00
		aes_csr_aliasing	3.0	904.495861	2	2	100.00
		aes_same_csr_outstanding	2.0	138.670213	2	2	100.00
		aes_csr_mem_rw_with_rand_reset	2.0	107.037073	2	2	100.00
		aes_wake_up	3.0	60.501110999999995	2	2	100.00
		aes_nist_vectors	9.0	255.778579	2	2	100.00
		aes_deinit	5.0	198.5733	2	2	100.00
		aes_man_cfg_err	2.0	169.32800500000002	2	2	100.00
		aes_readability	3.0	57.697089999999996	2	2	100.00
		aes_smoke	3.0	90.721783	2	2	100.00
		aes_config_error	4.0	365.95738400000005	2	2	100.00
		aes_stress	4.0	78.424694	2	2	100.00
		aes_b2b	10.0	490.931328	2	2	100.00
		aes_clear	3.0	248.975402	2	2	100.00
		aes_alert_reset	3.0	128.143463	2	2	100.00
		aes_sideload	4.0	343.95883899999995	2	2	100.00
		aes_reseed	4.0	91.38692	2	2	100.00
		aes_fi	3.0	134.090203	2	2	100.00
		aes_control_fi	2.0	49.839771999999996	2	2	100.00
		aes_cipher_fi	2.0	70.764218	2	2	100.00
		aes_ctr_fi	2.0	48.92567	2	2	100.00
		aes_core_fi	28.0	10011.489226	1	2	50.00
		aes_stress_all	20.0	1323.067382	2	2	100.00
		aes_stress_all_with_rand_reset	10.0	858.6793220000001	0	2	0.00
		aes_sec_cm	9.0	1301.114334	2	2	100.00
		aes_alert_test	2.0	58.60485	2	2	100.00
		csrng_tl_errors	3.0	68.014702	1	1	100.00
		csrng_tl_intg_err	4.0	67.527328	1	1	100.00
		csrng_intr_test	2.0	33.415447	1	1	100.00
		csrng_csr_hw_reset	2.0	15.96323	1	1	100.00
		csrng_csr_rw	2.0	55.330057000000004	1	1	100.00
		csrng_csr_bit_bash	14.0	367.92674300000004	1	1	100.00
		csrng_csr_aliasing	3.0	64.09056	1	1	100.00
		csrng_same_csr_outstanding	2.0	24.528934	1	1	100.00
		csrng_csr_mem_rw_with_rand_reset	2.0	35.254587	1	1	100.00
		csrng_smoke	3.0	25.499253	1	1	100.00
		csrng_cmds	39.0	1956.357973	1	1	100.00
		csrng_stress_all	316.0	5624.476966	1	1	100.00
		csrng_intr	4.0	99.084694	1	1	100.00
		csrng_alert	8.0	265.85258899999997	1	1	100.00
		csrng_err	2.0	22.915473000000002	1	1	100.00
		csrng_regwen	2.0	11.345049999999999	1	1	100.00
		csrng_stress_all_with_rand_reset	198.0	9770.542057	1	1	100.00
		csrng_sec_cm	4.0	239.409992	1	1	100.00
		csrng_alert_test	2.0	49.591758	1	1	100.00
		entropy_src_tl_errors	3.0	81.647044	1	1	100.00
		entropy_src_tl_intg_err	3.0	110.750362	1	1	100.00
		entropy_src_intr_test	2.0	35.739470999999995	1	1	100.00
		entropy_src_csr_hw_reset	2.0	53.394433	1	1	100.00
		entropy_src_csr_rw	2.0	77.275832	1	1	100.00
		entropy_src_csr_bit_bash	4.0	854.94228	1	1	100.00
		entropy_src_csr_aliasing	4.0	277.445753	1	1	100.00
		entropy_src_same_csr_outstanding	3.0	284.418156	1	1	100.00
		entropy_src_csr_mem_rw_with_rand_reset	2.0	67.255148	1	1	100.00
		entropy_src_smoke	2.0	35.599447	1	1	100.00
		entropy_src_rng	37.0	8120.089002000001	1	1	100.00
		entropy_src_rng_max_rate	266.0	8020.517891999999	1	1	100.00
		entropy_src_rng_with_xht_rsps	48.0	11045.727065	1	1	100.00
		entropy_src_stress_all	323.0	19261.793116999997	1	1	100.00
		entropy_src_fw_ov	233.0	12023.976254000001	1	1	100.00
		entropy_src_fw_ov_contiguous	3.0	108.69205199999999	1	1	100.00
		entropy_src_intr	2.0	189.085632	1	1	100.00
		entropy_src_functional_alerts	5.0	208.589366	1	1	100.00
		entropy_src_cfg_regwen	2.0	25.877805	1	1	100.00
		entropy_src_functional_errors	3.0	166.71717	1	1	100.00
		entropy_src_sec_cm	3.0	105.773791	1	1	100.00
		entropy_src_alert_test	2.0	18.383216	1	1	100.00
		otbn_smoke	12.0	56.79316	0	1	0.00
		otbn_single	10.0	134.26815100000002	0	1	0.00
		otbn_multi	69.0	934.051552	0	1	0.00
		otbn_reset	16.0	226.918651	0	1	0.00
		otbn_multi_err	38.0	336.564029	0	1	0.00
		otbn_imem_err	14.0	63.0976	0	1	0.00
		otbn_dmem_err	6.0	39.286391	0	1	0.00
		otbn_escalate	9.0	26.819236	0	1	0.00
		otbn_alu_bignum_mod_err	8.0	231.13478800000001	0	1	0.00
		otbn_controller_ispr_rdata_err	9.0	68.550411	0	1	0.00
		otbn_mac_bignum_acc_err	10.0	33.427381000000004	0	1	0.00
		otbn_rf_bignum_intg_err	8.0	57.384198	0	1	0.00
		otbn_rf_base_intg_err	6.0	49.28905	0	1	0.00
		otbn_stress_all	31.0	419.025158	0	1	0.00
		otbn_stress_all_with_rand_reset	338.0	1579.776115	0	1	0.00
		otbn_zero_state_err_urnd	5.0	30.802772	1	1	100.00
		otbn_illegal_mem_acc	8.0	59.072306	1	1	100.00
		otbn_sw_errs_fatal_chk	8.0	456.287626	0	1	0.00
		otbn_pc_ctrl_flow_redun	8.0	36.643637999999996	1	1	100.00
		otbn_rnd_sec_cm	38.0	836.135914	0	1	0.00
		otbn_ctrl_redun	5.0	20.908868	0	1	0.00
		otbn_sec_wipe_err	4.0	30.769527999999998	1	1	100.00
		otbn_urnd_err	5.0	16.120991	1	1	100.00
		otbn_sw_no_acc	7.0	52.937222	0	1	0.00
		otbn_mem_gnt_acc_err	5.0	38.280981	1	1	100.00
		otbn_stack_addr_integ_chk	6.0	14.644568999999999	0	1	0.00
		otbn_partial_wipe	4.0	33.016023999999994	1	1	100.00
		otbn_sec_cm	156.0	4395.677808	1	1	100.00
		otbn_alert_test	3.0	57.496961000000006	1	1	100.00
		otbn_passthru_mem_tl_intg_err	3.0	2.055029	0	1	0.00
		otbn_tl_errors	4.0	261.69327	1	1	100.00
		otbn_tl_intg_err	32.0	230.220531	1	1	100.00
		otbn_intr_test	3.0	52.054835	1	1	100.00
		otbn_mem_walk	32.0	361.635853	1	1	100.00
		otbn_mem_partial_access	12.0	449.82901	1	1	100.00
		otbn_csr_hw_reset	3.0	41.816978999999996	1	1	100.00
		otbn_csr_rw	2.0	12.457669	1	1	100.00
		otbn_csr_bit_bash	5.0	40.723713000000004	1	1	100.00
		otbn_csr_aliasing	3.0	40.98079	1	1	100.00
		otbn_same_csr_outstanding	4.0	30.349356	1	1	100.00
		otbn_csr_mem_rw_with_rand_reset	5.0	67.507974	1	1	100.00
		chip_sival_flash_info_access	132.17	0.0	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	360.38	0.0	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	2024.72	0.0	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	116.38	0.0	1	1	100.00
		chip_sw_otp_ctrl_descrambling	155.75	0.0	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	216.61	0.0	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.901758	0.0	0	1	0.00
		chip_sw_flash_ctrl_write_clear	192.59	0.0	1	1	100.00
		TOTAL			1418	1546	91.72

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
79.93	94.46	89.42	91.32	57.14	93.81	96.12	37.21

Failure Buckets

• Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 12 failures:

  • Test lc_ctrl_state_failure has 2 failures.

    • 0.lc_ctrl_state_failure.27778749632205863556609577742705456310901030470127461810968438129656600052810
      Line 217, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  12046972 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  12046972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_state_failure.74497405433307408092291174239226938835313113857205126622283397893754832540201
      Line 219, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  10735325 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  10735325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_state_post_trans has 2 failures.

    • 0.lc_ctrl_state_post_trans.704497693800046453593826029939978687492566734935456002490967603394099413453
      Line 396, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  21313140 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  21313140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_state_post_trans.8510178392633002193572089796022088287494051812108505451451677061420910302051
      Line 257, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 172150069 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 172150069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_state_failure has 2 failures.

    • 0.lc_ctrl_jtag_state_failure.52671486231380939760759857306531793181016349781306074653122905167802832328872
      Line 440, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  82832191 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  82832191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_jtag_state_failure.2399570644676828593211425472098221265101060332413521115213952954799442304609
      Line 242, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 133648101 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 133648101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_state_post_trans has 2 failures.

    • 0.lc_ctrl_jtag_state_post_trans.48014388963746602301512746186500402759251301516314005461007833851512730943752
      Line 193, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  95856594 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  95856594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.lc_ctrl_jtag_state_post_trans.57100765590610633412606697686742134665366431752123580220158161631497908175554
      Line 289, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @  86294593 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @  86294593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 0.lc_ctrl_stress_all.49682539924126827214548277458701656367913890825292046280017649063968451119152
      Line 14874, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 47089185262 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 47089185262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 3 more tests.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.344058945074650441041319336879301550983804373101679639562931193060967911026
      Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.92221114279466404853034126565580273881526822306312383515075816856848407603615
      Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

        UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.62927444509696962624121970435163684921521355279157004974160689486125698817742
      Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.61855579950590647091817841847542148721965445232639512224190751206534997288710
      Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.104247788780787523824133078351594587935904389862236107133103154337091884620082
      Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

        UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 6 more tests.

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@*_*.mnemonic_cp) is an illegal value. has 6 failures:

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.100469526371548268923134665160022135275068090638012266921599899327817777666552
      Line 151, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 58291552 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 58291552 PS + 24) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 58331552 PS + 26) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 58331552 PS + 26) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1270):(Time: 58331552 PS + 26) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@4220_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_imem_err has 1 failures.

    • 0.otbn_imem_err.19595918038177982783104586000500933603729981148073953002551774249346183081567
      Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_imem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 27410400 PS + 19) Sampled value (7564396) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 27420926 PS + 23) Sampled value (7564396) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 27420926 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 27420926 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 27431452 PS + 21) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_mac_bignum_acc_err has 1 failures.

    • 0.otbn_mac_bignum_acc_err.22735274893716382649473338189411344927729452578645053856321920285443134625444
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 17964712 PS + 30) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 17964712 PS + 30) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 17975465 PS + 25) Sampled value (7892850) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 17975465 PS + 25) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1344):(Time: 17975465 PS + 25) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@4223_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_rf_bignum_intg_err has 1 failures.

    • 0.otbn_rf_bignum_intg_err.55944353896445690837548105836771644975432708725617999263784070520329485369833
      Line 116, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 4121620 PS + 20) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4131721 PS + 21) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 4131721 PS + 21) Sampled value (1936875881) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 4131721 PS + 21) Sampled value (1936875881) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 4141822 PS + 25) Sampled value (1936875881) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_stress_all has 1 failures.

    • 0.otbn_stress_all.98810675117553718824718557096146889554634298224531278405217814186289635213511
      Line 141, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 13957601 PS + 22) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1363):(Time: 13957601 PS + 22) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_addsub_cg@4226_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 13997601 PS + 20) Sampled value (7566690) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 13997601 PS + 20) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 13997601 PS + 20) Sampled value (2020569705) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4217_1.mnemonic_cp) is an illegal value.
      

  • ... and 1 more tests.

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@*_*.mnemonic_cp) is an illegal value. has 5 failures:

  • Test otbn_single has 1 failures.

    • 0.otbn_single.7731533399374120196744287359997251727446491572773327512574832308733197193311
      Line 117, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_single/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 48028151 PS + 26) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 48068151 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 48068151 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1314):(Time: 48068151 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_s_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 48068151 PS + 23) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_multi_err has 1 failures.

    • 0.otbn_multi_err.8448683318218005159660960599645020166716591715827587129054513707150198888118
      Line 199, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 8110871 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 8131704 PS + 14) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 8131704 PS + 14) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1122):(Time: 8131704 PS + 14) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@4213_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1956):(Time: 8131704 PS + 14) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bn_xid_cg@4247_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.14020852745019138710130784475792875559547646766835199046436898028668645558393
      Line 141, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 11094150 PS + 23) Sampled value (7303785) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4219_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 11094150 PS + 23) Sampled value (7303785) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4236_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 11104354 PS + 27) Sampled value (7303785) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4202_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 11104354 PS + 27) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4202_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 11104354 PS + 27) Sampled value (7565921) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4224_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_sw_errs_fatal_chk has 1 failures.

    • 0.otbn_sw_errs_fatal_chk.57314909907777452372785313901153224234608466085170877693642392921724480264881
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 319087626 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 319287626 PS + 33) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 319287626 PS + 33) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 319287626 PS + 33) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 319687626 PS + 27) Sampled value (7565932) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

  • Test otbn_rnd_sec_cm has 1 failures.

    • 0.otbn_rnd_sec_cm.88087845064783632393188777099430814189194824199712085342418737502373790355930
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 39129578 PS + 21) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 39129578 PS + 21) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 39171245 PS + 23) Sampled value (27767) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 39171245 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 39171245 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.80237231562300595139986601689391321272976773914777204999226154353823302591403
      Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.66937508070766557262452669013322386954269642478361529778316604639874918172113
      Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

        UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.12129516943615810998214740984931206818284023623264064259256381071692245147009
      Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.6270450034221561668736412923709659678842944598879940831122521936151768784027
      Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.43886896894918764560275036198211608709206440378659597638775234325709774428498
      Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

        UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test rv_dm_sba_tl_access has 1 failures.

    • 0.rv_dm_sba_tl_access.30700694875430232936034793335092883665650489748874125912237324643230018236240
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_delayed_resp_sba_tl_access has 1 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.8107957257941149484472031834090598799451960440350634245353842030030332182707
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_bad_sba_tl_access has 1 failures.

    • 0.rv_dm_bad_sba_tl_access.89024201173662594406945095654764973462931501744422817083819625828992840519747
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_autoincr_sba_tl_access has 1 failures.

    • 0.rv_dm_autoincr_sba_tl_access.49743141114033108125895455729281390223508838261766555296104993533842691717518
      Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(rstreqs[*] && (reset_cause == HwReq))' has 4 failures:

  • Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.

    • 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.35285105048786438911591158669471766042218261666498133893100068333603367648505
      Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log

            Offending '(rstreqs[0] && (reset_cause == HwReq))'
        UVM_ERROR @ 5092.720000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
        UVM_INFO @ 5092.720000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.73092276484413251191231220982382350597117524962256915262731758426269887293673
      Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log

            Offending '(rstreqs[1] && (reset_cause == HwReq))'
        UVM_ERROR @ 10040.292500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
        UVM_INFO @ 10040.292500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.

    • 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.43352356771404197764392168315563473026349633181120368958494195307153429622711
      Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log

            Offending '(rstreqs[1] && (reset_cause == HwReq))'
        UVM_ERROR @ 5671.084000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
        UVM_INFO @ 5671.084000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.2149205901838270132175879650113000207680225726137385424208928230856778823093
      Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

            Offending '(rstreqs[1] && (reset_cause == HwReq))'
        UVM_ERROR @ 8075.656000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
        UVM_INFO @ 8075.656000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.119092512016958124952653169213074895578747646961059803158868292592179720345
      Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.72226862159071767584342166536705198868327358554043015986978174382560114944555
      Line 430, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.59883916046987169131977568286577147231639209536492941791112694130563735773759
      Line 440, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.18374548955426699204112003381834179317727185847877011267521150472980469716776
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  19513067 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  19513067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.97143825684791749459106121711850190879960768441827077691022095888736453871245
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @   3596201 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @   3596201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire has 2 failures:

  • Test pwrmgr_tl_intg_err has 1 failures.

    • 0.pwrmgr_tl_intg_err.65093618369649128841233443742053405718642768822918610856171896378954338099335
      Line 75, in log /nightly/current_run/scratch/master/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest/run.log

        UVM_ERROR @  16330669 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
        UVM_INFO @  16330669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_sec_cm has 1 failures.

    • 0.pwrmgr_sec_cm.67332338961455660141037906092799998037856162071323779563214278991644750271952
      Line 75, in log /nightly/current_run/scratch/master/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest/run.log

        UVM_ERROR @  17985943 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
        UVM_INFO @  17985943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 2 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.86982043565577383729382504857875231894733738530737697854841711839506128532080
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

  • Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_pings.92855735523472006420586481332309781895893976471947956906446373088237761556289
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log

        Job timed out after 240 minutes
      

• UVM_WARNING [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory. has 2 failures:

  • Test usbdev_stress_all_with_rand_reset has 1 failures.

    • 0.usbdev_stress_all_with_rand_reset.40153122560173443631513648975963310831270930193855967271447723392335411267107
      Line 76, in log /nightly/current_run/scratch/master/usbdev-sim-vcs/0.usbdev_stress_all_with_rand_reset/latest/run.log

        UVM_WARNING @  12514091 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
        UVM_INFO @  12514091 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
        #### Factory Configuration (*)
      
        No instance overrides are registered with this factory
      

  • Test usbdev_stress_all has 1 failures.

    • 0.usbdev_stress_all.62052804873114658683135886793359832493952026077551979742462750781984345020145
      Line 75, in log /nightly/current_run/scratch/master/usbdev-sim-vcs/0.usbdev_stress_all/latest/run.log

        UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
        UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
        #### Factory Configuration (*)
      
        No instance overrides are registered with this factory
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.2716006874971991772401886792949246856961469940633903815408132103695408745813
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  16728318 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  16728318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.sram_ctrl_sec_cm.110515634991064732733440152458302276344849390455988922647349890729336358994296
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  25844862 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  25844862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.79028657352160966934817406084278674935175873834282262452879332910833014168268
      Line 235, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 20431759ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 20431759ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 20431759ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 0.rom_ctrl_sec_cm.109404229653429075485275464874007542890972391397876864007915409796427636609339
      Line 128, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 54062941ps failed at 54062941ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 54102941ps failed at 54102941ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@*_*.mnemonic_cp) is an illegal value. has 2 failures:

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.105843422850514366046523172700259178242240269718100583914269104412451367672266
      Line 115, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 16733671 PS + 23) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 16770708 PS + 20) Sampled value (1936878697) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 16770708 PS + 20) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1344):(Time: 16770708 PS + 20) Sampled value (27705693569249906) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_wcsr_cg@4223_1.mnemonic_cp) is an illegal value.
        UVM_INFO @  24955885 ps: (otbn_base_vseq.sv:495) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq]
      

  • Test otbn_sw_no_acc has 1 failures.

    • 0.otbn_sw_no_acc.70354855843305640951580216891278289791187293499805041734334479019315006988376
      Line 103, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_no_acc/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1223):(Time: 27109490 PS + 23) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_is_cg@4217_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 27143973 PS + 19) Sampled value (1936485481) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 27143973 PS + 19) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 27143973 PS + 19) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1462):(Time: 27143973 PS + 19) Sampled value (6385252) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_log_binop_cg@4233_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@*_*.mnemonic_cp) is an illegal value. has 2 failures:

  • Test otbn_dmem_err has 1 failures.

    • 0.otbn_dmem_err.107518065599293933639612840153789291039410897927359218427320104254009262698917
      Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1270):(Time: 17077920 PS + 26) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@4220_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 17119587 PS + 20) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 17119587 PS + 20) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1314):(Time: 17119587 PS + 20) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_s_cg@4222_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1488):(Time: 17119587 PS + 20) Sampled value (29559) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_xw_cg@4234_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_alu_bignum_mod_err has 1 failures.

    • 0.otbn_alu_bignum_mod_err.46995719489905261769517914021308535944597700095391142727929671957575446859240
      Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1270):(Time: 18033784 PS + 27) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_loopi_cg@4220_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 18077262 PS + 19) Sampled value (465726042217) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 18077262 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1158):(Time: 18077262 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@4214_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1564):(Time: 18077262 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bxx_cg@4235_1.mnemonic_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@*_*.mnemonic_cp) is an illegal value. has 2 failures:

  • Test otbn_rf_base_intg_err has 1 failures.

    • 0.otbn_rf_base_intg_err.101323499502517017914356438069112795246893038989850791230231715683734141824940
      Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1158):(Time: 15970484 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@4214_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1564):(Time: 15970484 PS + 19) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bxx_cg@4235_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 16050484 PS + 25) Sampled value (6450789) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 16050484 PS + 25) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1292):(Time: 16050484 PS + 25) Sampled value (28530) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_r_cg@4221_1.mnemonic_cp) is an illegal value.
      

  • Test otbn_ctrl_redun has 1 failures.

    • 0.otbn_ctrl_redun.46741807644488207898405134646267329596007343851466142249030438911620267785664
      Line 104, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1158):(Time: 8051218 PS + 19) Sampled value (6448497) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_b_cg@4214_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1564):(Time: 8051218 PS + 19) Sampled value (6448497) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bxx_cg@4235_1.mnemonic_cp) is an illegal value.
        UVM_INFO @  20908868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 2 failures:

  • Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

    • 0.chip_sw_pwrmgr_sleep_wake_5_bug.53636631562524271261934801047729188652335180945378357414431437758994317578246
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
        ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
        INFO: Elapsed time: 0.558s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_self_hash has 1 failures.

    • 0.rom_e2e_self_hash.46266132023407096427766973935655393828327801359473548758973091383532070694683
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
        ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
        INFO: Elapsed time: 0.155s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.6988091472230063953764746738087239892105567507362968308831048883702092772174
      Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.96509373847863501418840340408338316967738457907161080196315312579948012647565
      Line 459, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log

        UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.16985640188117167264601940153988998980225770897329004034369567296360624197465
      Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.18879140475338323543416026305939826509965073750635619465782440567400372086714
      Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log

        UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:

  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.17927222511232943598163215233017046293698767244162334326560956304472246261995
      Line 75, in log /nightly/current_run/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  35968214 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @  35968214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.57827809768969974264934131742026522933389258841309364807962144130206784155707
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 921941784 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 38,                                 clk_pulses: 0
        UVM_ERROR @ 921983451 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 922025118 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 922066785 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 922108452 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.4117182716399422878919088850957975510121689493237555350045874718961360129590
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2261462 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[90])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2261462 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2261462 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[986])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.115606071186997535976893223209786435801893688137394537742941740448796477921311
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3562795 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x58e78c [10110001110011110001100] vs 0x0 [0])
        UVM_ERROR @   3637795 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x152ffa [101010010111111111010] vs 0x0 [0])
        UVM_ERROR @   3653795 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x887c73 [100010000111110001110011] vs 0x0 [0])
        UVM_ERROR @   3683795 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe0f37 [11100000111100110111] vs 0x0 [0])
        UVM_ERROR @   3724795 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x48eb95 [10010001110101110010101] vs 0x0 [0])
      

• UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*]) has 1 failures:

  • Test spi_device_flash_mode has 1 failures.

    • 0.spi_device_flash_mode.46929394475957872723640207012277162857077960720712243501476388932614416136620
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest/run.log

        UVM_ERROR @ 4085674105 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 4085674105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.13216650070687078883848835106380975828121863902173008957488020788957677538777
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2304779503 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2304779503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.59780699494421537988339682611626916558789906985199129910867782800942040928017
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 145186633 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 8 [0x8])
        UVM_INFO @ 145186633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.13544630677061224225233678221574112522716759013968107130713835301016794550350
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 366774446 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 366774446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.75019865170052098306817138266235362047014458262395839168814970671091485224290
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 625963246 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 625963246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.8318494167134692938799369696830916626894821146606260907696843946170495814874
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 403764245 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 403764245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.103844485212198810687202264537625006675793423303896025217867567081330723555736
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45545035 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45545035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.19603655385910631683192907174691088647258673037644790506280353376459326182356
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 106237540 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe9133904) == 0x1
        UVM_INFO @ 106237540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 0.pwrmgr_escalation_timeout.234445453042064877450261780272293021309267987148679608383630486172385410323
      Line 72, in log /nightly/current_run/scratch/master/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  97041251 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
        UVM_INFO @  97041251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5776) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tap_fsm_rand_reset has 1 failures.

    • 0.rv_dm_tap_fsm_rand_reset.86344028062914986553207823563826710807004296450599835821427491212938520100111
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

        UVM_ERROR @  48043075 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5776) { a_addr: 'ha0f2f5e8  a_data: 'h5e9e2b67  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc8  a_opcode: 'h4  a_user: 'h1928a  d_param: 'h0  d_source: 'hc8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  48043075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@53404) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_tl_errors has 1 failures.

    • 0.rv_dm_tl_errors.2414219803253670911215259978470447596779124172853481409301489141647404703692
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

        UVM_ERROR @ 347522410 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@53404) { a_addr: 'hcdf94364  a_data: 'h6a5bb7f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hed  a_opcode: 'h4  a_user: 'h18d0d  d_param: 'h0  d_source: 'hed  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 347522410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5844) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_dm_csr_mem_rw_with_rand_reset.6869170890644840837089596021954360352680540077281355448617006267594984981020
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  62340313 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5844) { a_addr: 'hb694720  a_data: 'h4ecedec6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h95  a_opcode: 'h4  a_user: 'h18a35  d_param: 'h0  d_source: 'h95  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  62340313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5650) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.55824916275418492308258000311575370471404492622189957175156975947183284026741
      Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  16044704 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5650) { a_addr: 'h5ba8d48c  a_data: 'hf5863453  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1bb4a  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @  16044704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.36988518157276545790766280674720605638763358483082826485376129044215954490598
      Line 2011, in log /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8588690784 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8588690784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.18562665894001869897106263492903579645313337848800947972061883292957844075031
      Line 93, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10114770886 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc965c000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
        UVM_INFO @ 10114770886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.29068287448546215145795962845484697046206828400132949171394741484607775330639
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10114187068 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa43383d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
        UVM_INFO @ 10114187068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.64081272836607017977780110104538778070405355922808076668857016558548149787086
      Line 288, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2629088891 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2629090338 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2629090338 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 5/10
        UVM_INFO @ 2629190338 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.55142871521476957442259163989733924940272817055427733235833538334255301862808
      Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.83127168725749256232215397284359839953827307496220110680944937452935771386725
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23549421 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7c) != exp (0xa)
        UVM_INFO @  23549421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.99312871417499794775402658329553224667532686861142216647161736046932814175184
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  29100823 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  29100823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 0.alert_handler_ping_timeout.45509576754854780681932895199641790940097623503669200074792795766694686333117
      Line 77, in log /nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 1843715889 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1843715889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* has 1 failures:

  • Test otp_ctrl_dai_errs has 1 failures.

    • 0.otp_ctrl_dai_errs.81908934772724995887643932016050759219525077695386120024836392792615406715866
      Line 1840, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log

        UVM_ERROR @ 382847911 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
        UVM_INFO @ 382847911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1143) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 1 failures:

  • Test otp_ctrl_check_fail has 1 failures.

    • 0.otp_ctrl_check_fail.81628043376875604603446101121056404334211818190550216998236307644237435802958
      Line 2601, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 361946997 ps: (otp_ctrl_scoreboard.sv:1143) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 361946997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.100071666069097314917689417693954146189438580536976518671513584735265685211158
      Line 96, in log /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105913679 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @ 105913679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.98377369510635147896221849576118389231434871347773099932797386755165587772091
      Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10011489226 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10011489226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.110746623379666945497868186184619116621870425774192433647071140997947962105821
      Line 648, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 858679322 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 858679322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.17458287177207388377217761712094965424759377437383657623903876158182433148331
      Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  10677605 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  10677605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_smoke has 1 failures.

    • 0.otbn_smoke.28582670878332733878074547815311313400715946240491313389272810374407529210500
      Line 120, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1332):(Time: 34905540 PS + 23) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_u_cg@4224_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 34915744 PS + 21) Sampled value (7107945) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 34915744 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1199):(Time: 34915744 PS + 21) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_i_cg@4216_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 34925948 PS + 23) Sampled value (1633969257) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@*_*.csr_cp) is an illegal value. has 1 failures:

  • Test otbn_escalate has 1 failures.

    • 0.otbn_escalate.58199176377360944901917235698484651363794956555468723702286754818181701456781
      Line 106, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 4531320 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 4711320 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 5031320 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 5131320 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 564):(Time: 5271320 PS + 17) Sampled value (8591112127431472442413084276077) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::ext_csr_wr_operational_state_cg@4191_1.csr_cp) is an illegal value.
      

• xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@*_*.mnemonic_cp) is an illegal value. has 1 failures:

  • Test otbn_controller_ispr_rdata_err has 1 failures.

    • 0.otbn_controller_ispr_rdata_err.99672675754382556518331428445682174731698906485752951728965004157026362506822
      Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/run.log

        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1122):(Time: 10702679 PS + 29) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnxid_cg@4213_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 1956):(Time: 10702679 PS + 29) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::insn_bn_xid_cg@4247_1.mnemonic_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 720):(Time: 10712988 PS + 25) Sampled value (108225364781412) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.last_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 727):(Time: 10712988 PS + 25) Sampled value (108225365243234) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4199_1.cur_cp) is an illegal value.
        xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 790):(Time: 10712988 PS + 25) Sampled value (108225365243234) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::enc_bnaf_cg@4201_1.mnemonic_cp) is an illegal value.
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 0.otbn_passthru_mem_tl_intg_err.7357372580775460682574534979423996447552539488212138223752483004652082378842
      Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   2055029 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @   2055029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34263) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.42914109322893511085565432499656313109926205572479338202155770747333531301261
      Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 1897.860010 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34263) { a_addr: 'h107c4  a_data: 'h2e6ef1b1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h18d37  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 1897.860010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33033) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.67842320837590590607023639871909228069698342973542146019034973241825595638341
      Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2743.867524 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33033) { a_addr: 'h10454  a_data: 'h1c09fc7e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h19574  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2743.867524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 0.chip_sw_all_escalation_resets.44762148596830416235427797729071535565301583949563264989020492561203885789103
      Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3056.352352 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
        UVM_INFO @ 3056.352352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.31581585549017867764748124992623712636036709534897266689036739594164360227680
      Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3734.955702 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3734.955702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:

  • Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.

    • 0.chip_sw_otp_ctrl_lc_signals_rma.40751257774611638588127643311154500116866265003123509497837597418612927638747
      Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log

        UVM_ERROR @ 6277.116057 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
        UVM_INFO @ 6277.116057 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:

  • Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.

    • 0.chip_sw_otp_ctrl_rot_auth_config.88002580558832516366537730902220338679050334250690878131014739807759541533245
      Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log

        UVM_ERROR @ 21674.315460 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
        UVM_INFO @ 21674.315460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81829) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.62925504055396482899302634438362421774276869827378731147268546793876684254304
      Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 3915.486342 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81829) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3915.486342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.

    • 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.66683414263201280427814346545793405684713387905050339945044150720652485494193
      Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log

        UVM_ERROR @ 34259.256294 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 34259.256294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 0.chip_sw_alert_test.102589577259162039426076785582604053413585472677426469527094480727235531009512
      Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 3235.890601 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
        UVM_INFO @ 3235.890601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.37784144750637117612442753423133403242448350382214523682974208513079958898082
      Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 2881.570430 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 2881.570430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:

  • Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.

    • 0.chip_sw_rv_core_ibex_lockstep_glitch.82378502515445798573621974549975817812586931917273089997776192113443626389064
      Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

        UVM_FATAL @ 2761.785178 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
        UVM_INFO @ 2761.785178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 0.chip_sw_power_idle_load.38032622558019103445074199134732318323959869458552702426044634611650996553670
      Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 3956.842000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3956.842000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_sleep_load has 1 failures.

    • 0.chip_sw_power_sleep_load.89242522503503207043764339673551397051677467411796003435945054588675635087631
      Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

        UVM_ERROR @ 2797.782000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 2797.782000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:

  • Test chip_sw_ast_clk_rst_inputs has 1 failures.

    • 0.chip_sw_ast_clk_rst_inputs.73568294806605960666817938821965209717353618268984289503369036226556731488387
      Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        UVM_ERROR @ 16356.027432 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
        UVM_INFO @ 16356.027432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.83980980431184790296083623252052595258423037835046956724509560548833600834931
      Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.77509245027715488232933056521550563988473011451406887572939887224069008265625
      Line 456, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log

        UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) has 1 failures:

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.15560434756280634779044188366684731021881655160611372515458867491624248331765
      Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_ERROR @ 3892.657117 us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (0 [0x0] vs 2 [0x2])
        UVM_INFO @ 3892.657117 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.114385154089411805269757479310794402928677779042975309106216002794803475783242
      Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_ERROR @ 4217.112545 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
        UVM_INFO @ 4217.112545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:

  • Test rom_raw_unlock has 1 failures.

    • 0.rom_raw_unlock.18671168164984389968253025152908898131854386347831802265098911171304819218299
      Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

        UVM_FATAL @ 14431.883471 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
        UVM_INFO @ 14431.883471 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---