ADC_CTRL Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.690s	0.000us	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.920s	0.000us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.510s	0.000us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	73.450s	0.000us	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.150s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.290s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.510s	0.000us	1	1	100.00
		adc_ctrl_csr_aliasing	4.150s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	73.320s	0.000us	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	521.610s	0.000us	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	60.720s	0.000us	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	222.050s	0.000us	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	254.590s	0.000us	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	319.210s	0.000us	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	436.560s	0.000us	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	125.700s	0.000us	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.180s	0.000us	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	11.390s	0.000us	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	27.420s	0.000us	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	720.810s	0.000us	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.390s	0.000us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.690s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.260s	0.000us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.260s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.920s	0.000us	1	1	100.00
		adc_ctrl_csr_rw	1.510s	0.000us	1	1	100.00
		adc_ctrl_csr_aliasing	4.150s	0.000us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.400s	0.000us	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.920s	0.000us	1	1	100.00
		adc_ctrl_csr_rw	1.510s	0.000us	1	1	100.00
		adc_ctrl_csr_aliasing	4.150s	0.000us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.400s	0.000us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.540s	0.000us	1	1	100.00
		adc_ctrl_tl_intg_err	3.170s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.170s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.410s	0.000us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.79	99.02	95.45	100.00	89.19	98.51	95.95	50.44