AES/MASKED Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: `efa7857`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	98.898us	2	2	100.00
V1	smoke	aes_smoke	2.000s	98.326us	2	2	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	88.221us	2	2	100.00
V1	csr_rw	aes_csr_rw	2.000s	83.934us	2	2	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.000s	196.250us	2	2	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	99.402us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	70.583us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	83.934us	2	2	100.00
		aes_csr_aliasing	2.000s	99.402us	2	2	100.00
V1		TOTAL			14	14	100.00
V2	algorithm	aes_smoke	2.000s	98.326us	2	2	100.00
		aes_config_error	3.000s	80.850us	2	2	100.00
		aes_stress	5.000s	258.121us	2	2	100.00
V2	key_length	aes_smoke	2.000s	98.326us	2	2	100.00
		aes_config_error	3.000s	80.850us	2	2	100.00
		aes_stress	5.000s	258.121us	2	2	100.00
V2	back2back	aes_stress	5.000s	258.121us	2	2	100.00
		aes_b2b	16.000s	3299.967us	2	2	100.00
V2	backpressure	aes_stress	5.000s	258.121us	2	2	100.00
V2	multi_message	aes_smoke	2.000s	98.326us	2	2	100.00
		aes_config_error	3.000s	80.850us	2	2	100.00
		aes_stress	5.000s	258.121us	2	2	100.00
		aes_alert_reset	3.000s	122.527us	2	2	100.00
V2	failure_test	aes_man_cfg_err	3.000s	70.464us	2	2	100.00
		aes_config_error	3.000s	80.850us	2	2	100.00
		aes_alert_reset	3.000s	122.527us	2	2	100.00
V2	trigger_clear_test	aes_clear	7.000s	460.443us	2	2	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	309.399us	2	2	100.00
V2	reset_recovery	aes_alert_reset	3.000s	122.527us	2	2	100.00
V2	stress	aes_stress	5.000s	258.121us	2	2	100.00
V2	sideload	aes_stress	5.000s	258.121us	2	2	100.00
		aes_sideload	5.000s	586.709us	2	2	100.00
V2	deinitialization	aes_deinit	3.000s	106.821us	2	2	100.00
V2	stress_all	aes_stress_all	25.000s	1102.536us	2	2	100.00
V2	alert_test	aes_alert_test	2.000s	62.841us	2	2	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	574.272us	2	2	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	574.272us	2	2	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	88.221us	2	2	100.00
		aes_csr_rw	2.000s	83.934us	2	2	100.00
		aes_csr_aliasing	2.000s	99.402us	2	2	100.00
		aes_same_csr_outstanding	2.000s	57.207us	2	2	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	88.221us	2	2	100.00
		aes_csr_rw	2.000s	83.934us	2	2	100.00
		aes_csr_aliasing	2.000s	99.402us	2	2	100.00
		aes_same_csr_outstanding	2.000s	57.207us	2	2	100.00
V2		TOTAL			26	26	100.00
V2S	reseeding	aes_reseed	5.000s	85.806us	2	2	100.00
V2S	fault_inject	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	473.146us	2	2	100.00
V2S	tl_intg_err	aes_tl_intg_err	3.000s	395.292us	2	2	100.00
		aes_sec_cm	11.000s	2925.636us	2	2	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	395.292us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	122.527us	2	2	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	98.326us	2	2	100.00
		aes_stress	5.000s	258.121us	2	2	100.00
		aes_alert_reset	3.000s	122.527us	2	2	100.00
		aes_core_fi	3.000s	90.296us	2	2	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	306.997us	2	2	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	111.986us	2	2	100.00
		aes_stress	5.000s	258.121us	2	2	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	258.121us	2	2	100.00
		aes_sideload	5.000s	586.709us	2	2	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	111.986us	2	2	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	111.986us	2	2	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	111.986us	2	2	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	111.986us	2	2	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	111.986us	2	2	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	258.121us	2	2	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	258.121us	2	2	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	132.457us	2	2	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	132.457us	2	2	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	53.137us	2	2	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	132.457us	2	2	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	122.527us	2	2	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_ctr_fi	3.000s	57.336us	2	2	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	132.457us	2	2	100.00
		aes_control_fi	2.000s	65.732us	2	2	100.00
		aes_cipher_fi	2.000s	53.137us	2	2	100.00
V2S		TOTAL			22	22	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	21.000s	823.957us	0	2	0.00
V3		TOTAL			0	2	0.00
		TOTAL			62	64	96.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.12	95.80	90.64	97.14	90.18	97.99	95.56	98.21	79.88

Failure Buckets

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.14370661285297723734141084998214341084998095207037070921705321527110902735288
Line 412, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 283907587 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 283907587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

0.aes_stress_all_with_rand_reset.15318076912043705103627245317555778608829116562690863821037490649258849078337
Line 887, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 823956656 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 823956656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---