CSRNG Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 2.000s 26.759us 1 1 100.00
V1 csr_hw_reset csrng_csr_hw_reset 3.000s 22.143us 1 1 100.00
V1 csr_rw csrng_csr_rw 2.000s 15.798us 1 1 100.00
V1 csr_bit_bash csrng_csr_bit_bash 6.000s 292.263us 1 1 100.00
V1 csr_aliasing csrng_csr_aliasing 2.000s 23.215us 1 1 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 4.000s 273.121us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 2.000s 15.798us 1 1 100.00
csrng_csr_aliasing 2.000s 23.215us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 interrupts csrng_intr 7.000s 459.688us 1 1 100.00
V2 alerts csrng_alert 7.000s 88.759us 1 1 100.00
V2 err csrng_err 3.000s 21.398us 1 1 100.00
V2 cmds csrng_cmds 118.000s 10431.936us 1 1 100.00
V2 life cycle csrng_cmds 118.000s 10431.936us 1 1 100.00
V2 stress_all csrng_stress_all 90.000s 2422.420us 1 1 100.00
V2 intr_test csrng_intr_test 2.000s 34.481us 1 1 100.00
V2 alert_test csrng_alert_test 2.000s 17.038us 1 1 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 4.000s 63.019us 1 1 100.00
V2 tl_d_illegal_access csrng_tl_errors 4.000s 63.019us 1 1 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 3.000s 22.143us 1 1 100.00
csrng_csr_rw 2.000s 15.798us 1 1 100.00
csrng_csr_aliasing 2.000s 23.215us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.951us 1 1 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 3.000s 22.143us 1 1 100.00
csrng_csr_rw 2.000s 15.798us 1 1 100.00
csrng_csr_aliasing 2.000s 23.215us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.951us 1 1 100.00
V2 TOTAL 9 9 100.00
V2S tl_intg_err csrng_sec_cm 2.000s 51.441us 1 1 100.00
csrng_tl_intg_err 5.000s 271.507us 1 1 100.00
V2S sec_cm_config_regwen csrng_regwen 3.000s 36.158us 1 1 100.00
csrng_csr_rw 2.000s 15.798us 1 1 100.00
V2S sec_cm_config_mubi csrng_alert 7.000s 88.759us 1 1 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 90.000s 2422.420us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_updrsp_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_ctrl_mubi csrng_alert 7.000s 88.759us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 90.000s 2422.420us 1 1 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 7.000s 88.759us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 5.000s 271.507us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
csrng_sec_cm 2.000s 51.441us 1 1 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 7.000s 459.688us 1 1 100.00
csrng_err 3.000s 21.398us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 228.000s 15040.183us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.63 96.70 91.91 97.71 95.05 91.71 84.85 91.99 75.46