EDN Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	0.000us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.820s	0.000us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.800s	0.000us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.680s	0.000us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.860s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.350s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.800s	0.000us	1	1	100.00
		edn_csr_aliasing	0.860s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.180s	0.000us	1	1	100.00
V2	csrng_commands	edn_genbits	1.180s	0.000us	1	1	100.00
V2	genbits	edn_genbits	1.180s	0.000us	1	1	100.00
V2	interrupts	edn_intr	0.810s	0.000us	1	1	100.00
V2	alerts	edn_alert	1.080s	0.000us	1	1	100.00
V2	errs	edn_err	1.070s	0.000us	1	1	100.00
V2	disable	edn_disable	0.980s	0.000us	1	1	100.00
		edn_disable_auto_req_mode	1.140s	0.000us	1	1	100.00
V2	stress_all	edn_stress_all	1.100s	0.000us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	0.000us	1	1	100.00
V2	alert_test	edn_alert_test	0.890s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.950s	0.000us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.950s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.820s	0.000us	1	1	100.00
		edn_csr_rw	0.800s	0.000us	1	1	100.00
		edn_csr_aliasing	0.860s	0.000us	1	1	100.00
		edn_same_csr_outstanding	1.300s	0.000us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.820s	0.000us	1	1	100.00
		edn_csr_rw	0.800s	0.000us	1	1	100.00
		edn_csr_aliasing	0.860s	0.000us	1	1	100.00
		edn_same_csr_outstanding	1.300s	0.000us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_tl_intg_err	1.880s	0.000us	1	1	100.00
		edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.860s	0.000us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.080s	0.000us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.080s	0.000us	1	1	100.00
		edn_sec_cm	3.910s	0.000us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.080s	0.000us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.880s	0.000us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	66.720s	0.000us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.87	97.91	88.64	82.56	51.74	92.96	96.00	77.29