ENTROPY_SRC/RNG_4BITS Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 2.000s 24.620us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 2.000s 31.423us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 2.000s 17.982us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 7.000s 1331.976us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 3.000s 163.659us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 2.000s 84.595us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 2.000s 17.982us 1 1 100.00
entropy_src_csr_aliasing 3.000s 163.659us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 2.000s 24.620us 1 1 100.00
entropy_src_rng 109.000s 13057.449us 1 1 100.00
entropy_src_fw_ov 138.000s 17037.728us 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 138.000s 17037.728us 1 1 100.00
V2 rng_mode entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 288.000s 9080.413us 1 1 100.00
V2 health_checks entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2 conditioning entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2 interrupts entropy_src_rng 109.000s 13057.449us 1 1 100.00
entropy_src_intr 4.000s 613.567us 1 1 100.00
V2 alerts entropy_src_rng 109.000s 13057.449us 1 1 100.00
entropy_src_functional_alerts 5.000s 349.682us 1 1 100.00
V2 stress_all entropy_src_stress_all 302.000s 20035.147us 1 1 100.00
V2 functional_errors entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 3.000s 64.233us 1 1 100.00
V2 intr_test entropy_src_intr_test 2.000s 21.871us 1 1 100.00
V2 alert_test entropy_src_alert_test 2.000s 16.571us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 4.000s 159.624us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 4.000s 159.624us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 2.000s 31.423us 1 1 100.00
entropy_src_csr_rw 2.000s 17.982us 1 1 100.00
entropy_src_csr_aliasing 3.000s 163.659us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 97.505us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 2.000s 31.423us 1 1 100.00
entropy_src_csr_rw 2.000s 17.982us 1 1 100.00
entropy_src_csr_aliasing 3.000s 163.659us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 97.505us 1 1 100.00
V2 TOTAL 12 12 100.00
V2S tl_intg_err entropy_src_sec_cm 3.000s 100.311us 1 1 100.00
entropy_src_tl_intg_err 4.000s 401.264us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 109.000s 13057.449us 1 1 100.00
entropy_src_cfg_regwen 3.000s 17.117us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 109.000s 13057.449us 1 1 100.00
entropy_src_fw_ov 138.000s 17037.728us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
entropy_src_sec_cm 3.000s 100.311us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
entropy_src_sec_cm 3.000s 100.311us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 109.000s 13057.449us 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
entropy_src_sec_cm 3.000s 100.311us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
entropy_src_sec_cm 3.000s 100.311us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 3.000s 169.096us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 349.682us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 4.000s 401.264us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 38.000s 7116.074us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 22 22 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
88.27 97.00 92.41 98.03 93.00 76.12 95.83 84.16 51.52