HMAC Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	9.970s	0.000us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.950s	0.000us	1	1	100.00
V1	csr_rw	hmac_csr_rw	1.000s	0.000us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	4.190s	0.000us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.180s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.900s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	0.000us	1	1	100.00
		hmac_csr_aliasing	4.180s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	11.040s	0.000us	1	1	100.00
V2	back_pressure	hmac_back_pressure	66.290s	0.000us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	196.300s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	415.760s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	373.540s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	6.600s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	9.400s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	8.490s	0.000us	1	1	100.00
V2	burst_wr	hmac_burst_wr	10.040s	0.000us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	397.050s	0.000us	1	1	100.00
V2	error	hmac_error	11.140s	0.000us	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	21.150s	0.000us	1	1	100.00
V2	save_and_restore	hmac_smoke	9.970s	0.000us	1	1	100.00
		hmac_long_msg	11.040s	0.000us	1	1	100.00
		hmac_back_pressure	66.290s	0.000us	1	1	100.00
		hmac_datapath_stress	397.050s	0.000us	1	1	100.00
		hmac_burst_wr	10.040s	0.000us	1	1	100.00
		hmac_stress_all	9.710s	0.000us	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	9.970s	0.000us	1	1	100.00
		hmac_long_msg	11.040s	0.000us	1	1	100.00
		hmac_back_pressure	66.290s	0.000us	1	1	100.00
		hmac_datapath_stress	397.050s	0.000us	1	1	100.00
		hmac_wipe_secret	21.150s	0.000us	1	1	100.00
		hmac_test_sha256_vectors	196.300s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	415.760s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	373.540s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	6.600s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	9.400s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	8.490s	0.000us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	9.970s	0.000us	1	1	100.00
		hmac_long_msg	11.040s	0.000us	1	1	100.00
		hmac_back_pressure	66.290s	0.000us	1	1	100.00
		hmac_datapath_stress	397.050s	0.000us	1	1	100.00
		hmac_burst_wr	10.040s	0.000us	1	1	100.00
		hmac_error	11.140s	0.000us	1	1	100.00
		hmac_wipe_secret	21.150s	0.000us	1	1	100.00
		hmac_test_sha256_vectors	196.300s	0.000us	1	1	100.00
		hmac_test_sha384_vectors	415.760s	0.000us	1	1	100.00
		hmac_test_sha512_vectors	373.540s	0.000us	1	1	100.00
		hmac_test_hmac256_vectors	6.600s	0.000us	1	1	100.00
		hmac_test_hmac384_vectors	9.400s	0.000us	1	1	100.00
		hmac_test_hmac512_vectors	8.490s	0.000us	1	1	100.00
		hmac_stress_all	9.710s	0.000us	1	1	100.00
V2	stress_all	hmac_stress_all	9.710s	0.000us	1	1	100.00
V2	alert_test	hmac_alert_test	0.630s	0.000us	1	1	100.00
V2	intr_test	hmac_intr_test	0.670s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.220s	0.000us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.220s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.950s	0.000us	1	1	100.00
		hmac_csr_rw	1.000s	0.000us	1	1	100.00
		hmac_csr_aliasing	4.180s	0.000us	1	1	100.00
		hmac_same_csr_outstanding	1.080s	0.000us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.950s	0.000us	1	1	100.00
		hmac_csr_rw	1.000s	0.000us	1	1	100.00
		hmac_csr_aliasing	4.180s	0.000us	1	1	100.00
		hmac_same_csr_outstanding	1.080s	0.000us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_tl_intg_err	1.790s	0.000us	1	1	100.00
		hmac_sec_cm	0.940s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	1.790s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	9.970s	0.000us	1	1	100.00
V3	stress_reset	hmac_stress_reset	0.810s	0.000us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	85.390s	0.000us	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	2.740s	0.000us	1	1	100.00
		TOTAL			28	28	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.48	99.63	96.35	100.00	91.18	99.17	96.42	43.64