I2C Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	65.390s	0.000us	1	1	100.00
V1	target_smoke	i2c_target_smoke	18.370s	0.000us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	0.000us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.650s	0.000us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.970s	0.000us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.220s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.920s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.650s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.220s	0.000us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.980s	0.000us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2378.300s	0.000us	1	1	100.00
V2	host_maxperf	i2c_host_perf	63.200s	0.000us	1	1	100.00
V2	host_override	i2c_host_override	0.720s	0.000us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	74.880s	0.000us	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	27.030s	0.000us	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.960s	0.000us	1	1	100.00
		i2c_host_fifo_fmt_empty	17.260s	0.000us	1	1	100.00
		i2c_host_fifo_reset_rx	6.460s	0.000us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	61.410s	0.000us	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	18.340s	0.000us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.740s	0.000us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.070s	0.000us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	200.300s	0.000us	0	1	0.00
V2	target_maxperf	i2c_target_perf	6.210s	0.000us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	66.390s	0.000us	1	1	100.00
		i2c_target_intr_smoke	3.290s	0.000us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.910s	0.000us	1	1	100.00
		i2c_target_fifo_reset_tx	2.190s	0.000us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	65.620s	0.000us	1	1	100.00
		i2c_target_stress_rd	66.390s	0.000us	1	1	100.00
		i2c_target_intr_stress_wr	25.340s	0.000us	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.170s	0.000us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	59.440s	0.000us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.830s	0.000us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.620s	0.000us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.150s	0.000us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.060s	0.000us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	63.200s	0.000us	1	1	100.00
		i2c_host_perf_precise	2.010s	0.000us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	18.340s	0.000us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.790s	0.000us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.990s	0.000us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.070s	0.000us	1	1	100.00
		i2c_target_nack_txstretch	1.380s	0.000us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.270s	0.000us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.750s	0.000us	1	1	100.00
V2	alert_test	i2c_alert_test	0.770s	0.000us	1	1	100.00
V2	intr_test	i2c_intr_test	0.800s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.200s	0.000us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.200s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	0.000us	1	1	100.00
		i2c_csr_rw	0.650s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.220s	0.000us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	0.000us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	0.000us	1	1	100.00
		i2c_csr_rw	0.650s	0.000us	1	1	100.00
		i2c_csr_aliasing	1.220s	0.000us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	0.000us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_sec_cm	1.120s	0.000us	1	1	100.00
		i2c_tl_intg_err	1.040s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.040s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.750s	0.000us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.820s	0.000us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.700s	0.000us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.51	96.63	87.37	89.66	44.64	92.83	96.19	84.25

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.25111715383149048082340107651025489176475021982271784316754465005283690917176
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1486883159 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1486883159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.23961883222190767205231531579786093072074628888018998285923351115783264956617
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 316022279 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 316022279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.40446642200352539882658262144714043598727146733006657561038065894186971536278
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 104407959 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 104407959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.113554920834535664639039222820088131898595626383493346745094780015765646768521
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1627827547 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1627827547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.44607089595978405056528955046421737744111535496922077537543455273908408558894
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 161738102 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 210 [0xd2])
        UVM_INFO @ 161738102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:

  • Test i2c_target_stress_all has 1 failures.

    • 0.i2c_target_stress_all.18243080925842635981329328157573995309377944431854328604030097135920494930990
      Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

        UVM_FATAL @ 81132838761 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
        UVM_INFO @ 81132838761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---