KMAC/UNMASKED Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.340s	0.000us	2	2	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	0.000us	2	2	100.00
V1	csr_rw	kmac_csr_rw	1.430s	0.000us	2	2	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.140s	0.000us	2	2	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.250s	0.000us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.200s	0.000us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.430s	0.000us	2	2	100.00
		kmac_csr_aliasing	3.250s	0.000us	2	2	100.00
V1	mem_walk	kmac_mem_walk	0.900s	0.000us	2	2	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.350s	0.000us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2066.410s	0.000us	2	2	100.00
V2	burst_write	kmac_burst_write	779.440s	0.000us	2	2	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1793.630s	0.000us	2	2	100.00
		kmac_test_vectors_sha3_256	1344.760s	0.000us	2	2	100.00
		kmac_test_vectors_sha3_384	807.250s	0.000us	2	2	100.00
		kmac_test_vectors_sha3_512	970.230s	0.000us	2	2	100.00
		kmac_test_vectors_shake_128	2079.960s	0.000us	1	2	50.00
		kmac_test_vectors_shake_256	1287.170s	0.000us	2	2	100.00
		kmac_test_vectors_kmac	2.310s	0.000us	2	2	100.00
		kmac_test_vectors_kmac_xof	1.850s	0.000us	2	2	100.00
V2	sideload	kmac_sideload	164.190s	0.000us	2	2	100.00
V2	app	kmac_app	138.780s	0.000us	2	2	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	222.580s	0.000us	2	2	100.00
V2	entropy_refresh	kmac_entropy_refresh	244.200s	0.000us	2	2	100.00
V2	error	kmac_error	341.470s	0.000us	2	2	100.00
V2	key_error	kmac_key_error	3.730s	0.000us	2	2	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.870s	0.000us	2	2	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.390s	0.000us	2	2	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.470s	0.000us	2	2	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	44.850s	0.000us	2	2	100.00
V2	lc_escalation	kmac_lc_escalation	1.780s	0.000us	2	2	100.00
V2	stress_all	kmac_stress_all	939.680s	0.000us	2	2	100.00
V2	intr_test	kmac_intr_test	1.030s	0.000us	2	2	100.00
V2	alert_test	kmac_alert_test	0.980s	0.000us	2	2	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.110s	0.000us	2	2	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.110s	0.000us	2	2	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	0.000us	2	2	100.00
		kmac_csr_rw	1.430s	0.000us	2	2	100.00
		kmac_csr_aliasing	3.250s	0.000us	2	2	100.00
		kmac_same_csr_outstanding	1.830s	0.000us	2	2	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	0.000us	2	2	100.00
		kmac_csr_rw	1.430s	0.000us	2	2	100.00
		kmac_csr_aliasing	3.250s	0.000us	2	2	100.00
		kmac_same_csr_outstanding	1.830s	0.000us	2	2	100.00
V2		TOTAL			51	52	98.08
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.090s	0.000us	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.090s	0.000us	2	2	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.090s	0.000us	2	2	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.090s	0.000us	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.280s	0.000us	2	2	100.00
V2S	tl_intg_err	kmac_sec_cm	57.660s	0.000us	2	2	100.00
		kmac_tl_intg_err	3.880s	0.000us	2	2	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.880s	0.000us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.780s	0.000us	2	2	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.340s	0.000us	2	2	100.00
V2S	sec_cm_key_sideload	kmac_sideload	164.190s	0.000us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.090s	0.000us	2	2	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	57.660s	0.000us	2	2	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	57.660s	0.000us	2	2	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	57.660s	0.000us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.340s	0.000us	2	2	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.780s	0.000us	2	2	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	57.660s	0.000us	2	2	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	219.390s	0.000us	2	2	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.340s	0.000us	2	2	100.00
V2S		TOTAL			10	10	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	156.330s	0.000us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			79	80	98.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.56	97.53	93.90	100.00	63.64	95.89	97.74	92.23

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_test_vectors_shake_128 has 1 failures.

    • 0.kmac_test_vectors_shake_128.81196931292546342295354891450183355221730734027504741707792189213176763833255
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log

        UVM_ERROR @  91290098 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  91290098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---