OTBN Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 163.622us 0 1 0.00
V1 single_binary otbn_single 6.000s 71.731us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 26.945us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 35.532us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 134.653us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 92.707us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 110.997us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 35.532us 1 1 100.00
otbn_csr_aliasing 3.000s 92.707us 1 1 100.00
V1 mem_walk otbn_mem_walk 43.000s 1787.459us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 17.000s 1402.271us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 18.000s 225.299us 0 1 0.00
V2 multi_error otbn_multi_err 91.000s 442.178us 0 1 0.00
V2 back_to_back otbn_multi 77.000s 304.142us 0 1 0.00
V2 stress_all otbn_stress_all 71.000s 279.511us 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 146.869us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 4.000s 58.672us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 9.000s 189.066us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 17.573us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 40.612us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 3.000s 92.431us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 3.000s 92.431us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 26.945us 1 1 100.00
otbn_csr_rw 4.000s 35.532us 1 1 100.00
otbn_csr_aliasing 3.000s 92.707us 1 1 100.00
otbn_same_csr_outstanding 4.000s 40.346us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 26.945us 1 1 100.00
otbn_csr_rw 4.000s 35.532us 1 1 100.00
otbn_csr_aliasing 3.000s 92.707us 1 1 100.00
otbn_same_csr_outstanding 4.000s 40.346us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 6.000s 23.585us 0 1 0.00
otbn_dmem_err 9.000s 20.030us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 9.000s 100.467us 0 1 0.00
otbn_controller_ispr_rdata_err 6.000s 25.881us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 221.941us 0 1 0.00
otbn_urnd_err 16.000s 70.218us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 21.048us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 34.353us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 34.423us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 181.000s 4138.833us 1 1 100.00
otbn_tl_intg_err 10.000s 249.654us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 30.000s 215.419us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S prim_count_check otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 163.622us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 20.030us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 6.000s 23.585us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 10.000s 249.654us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 146.869us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 6.000s 23.585us 0 1 0.00
otbn_dmem_err 9.000s 20.030us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 58.672us 1 1 100.00
otbn_illegal_mem_acc 6.000s 21.048us 1 1 100.00
otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 6.000s 23.585us 0 1 0.00
otbn_dmem_err 9.000s 20.030us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 58.672us 1 1 100.00
otbn_illegal_mem_acc 6.000s 21.048us 1 1 100.00
otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 146.869us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 6.000s 23.585us 0 1 0.00
otbn_dmem_err 9.000s 20.030us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 58.672us 1 1 100.00
otbn_illegal_mem_acc 6.000s 21.048us 1 1 100.00
otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 37.774us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 40.137us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 19.000s 228.172us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 19.000s 228.172us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 51.337us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 10.000s 44.224us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 14.000s 240.511us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 14.000s 240.511us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 24.551us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 77.000s 304.142us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 7.000s 20.439us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 6.000s 71.731us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 181.000s 4138.833us 1 1 100.00
V2S TOTAL 9 20 45.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 212.000s 1129.680us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 21 41 51.22

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.44 97.69 70.16 96.89 77.53 55.25 87.18 78.31 95.30

Failure Buckets