PATTGEN Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: `efa7857`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	22.188us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	51.011us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	54.545us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	991.695us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	76.128us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	26.310us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	54.545us	1	1	100.00
		pattgen_csr_aliasing	1.000s	76.128us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	0.000s	0.000us	0	1	0.00
V2	cnt_rollover	cnt_rollover	10.000s	18880.467us	1	1	100.00
V2	error	pattgen_error	1.000s	30.714us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.000s	35.513us	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	13.864us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	20.966us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	122.683us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	122.683us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	51.011us	1	1	100.00
		pattgen_csr_rw	1.000s	54.545us	1	1	100.00
		pattgen_csr_aliasing	1.000s	76.128us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	119.906us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	51.011us	1	1	100.00
		pattgen_csr_rw	1.000s	54.545us	1	1	100.00
		pattgen_csr_aliasing	1.000s	76.128us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	119.906us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_sec_cm	1.000s	77.054us	1	1	100.00
		pattgen_tl_intg_err	2.000s	184.323us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	184.323us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	62.000s	5785.852us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	44.675us	1	1	100.00
		TOTAL			16	18	88.89

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.20	100.00	100.00	100.00	96.25	96.61	--	96.95	89.42

Failure Buckets

Job timed out after * minutes has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.98989557945998429221965978345314979484393856642198264006390114946084287576524
    Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.46004756910558020168089812482523556143431016936721705743687250244200851680311
Line 145, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 744647388 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 744653453 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 744653453 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 744796309 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]