ROM_CTRL/64KB Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.540s 0.000us 2 2 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.720s 0.000us 2 2 100.00
V1 csr_rw rom_ctrl_csr_rw 7.240s 0.000us 2 2 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.650s 0.000us 2 2 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.210s 0.000us 2 2 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.550s 0.000us 2 2 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.240s 0.000us 2 2 100.00
rom_ctrl_csr_aliasing 7.210s 0.000us 2 2 100.00
V1 mem_walk rom_ctrl_mem_walk 7.010s 0.000us 2 2 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.410s 0.000us 2 2 100.00
V1 TOTAL 16 16 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.770s 0.000us 2 2 100.00
V2 stress_all rom_ctrl_stress_all 28.000s 0.000us 2 2 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.030s 0.000us 2 2 100.00
V2 alert_test rom_ctrl_alert_test 7.100s 0.000us 2 2 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.950s 0.000us 2 2 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.950s 0.000us 2 2 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.720s 0.000us 2 2 100.00
rom_ctrl_csr_rw 7.240s 0.000us 2 2 100.00
rom_ctrl_csr_aliasing 7.210s 0.000us 2 2 100.00
rom_ctrl_same_csr_outstanding 10.090s 0.000us 2 2 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.720s 0.000us 2 2 100.00
rom_ctrl_csr_rw 7.240s 0.000us 2 2 100.00
rom_ctrl_csr_aliasing 7.210s 0.000us 2 2 100.00
rom_ctrl_same_csr_outstanding 10.090s 0.000us 2 2 100.00
V2 TOTAL 12 12 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.400s 0.000us 2 2 100.00
V2S tl_intg_err rom_ctrl_tl_intg_err 100.100s 0.000us 2 2 100.00
rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S prim_count_check rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.540s 0.000us 2 2 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.540s 0.000us 2 2 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.540s 0.000us 2 2 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 100.100s 0.000us 2 2 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
rom_ctrl_kmac_err_chk 13.030s 0.000us 2 2 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 97.130s 0.000us 2 2 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.400s 0.000us 2 2 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 459.890s 0.000us 2 2 100.00
V2S TOTAL 8 8 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 212.770s 0.000us 2 2 100.00
V3 TOTAL 2 2 100.00
TOTAL 38 38 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.54 99.59 97.47 99.90 100.00 98.91 96.80 97.14