RV_TIMER Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.330s	0.000us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.760s	0.000us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.630s	0.000us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.020s	0.000us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.700s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.750s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.630s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.660s	0.000us	0	1	0.00
V2	disabled	rv_timer_disabled	1.310s	0.000us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	630.550s	0.000us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	630.550s	0.000us	1	1	100.00
V2	stress	rv_timer_stress_all	1.110s	0.000us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.530s	0.000us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.730s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.720s	0.000us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.720s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.760s	0.000us	1	1	100.00
		rv_timer_csr_rw	0.630s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	0.000us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	0.000us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.760s	0.000us	1	1	100.00
		rv_timer_csr_rw	0.630s	0.000us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	0.000us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	0.000us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_tl_intg_err	1.320s	0.000us	1	1	100.00
		rv_timer_sec_cm	0.880s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.320s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	5.110s	0.000us	0	1	0.00
V3	max_value	rv_timer_max	0.640s	0.000us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	23.290s	0.000us	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.00	100.00	100.00	100.00	--	100.00	96.82	91.18

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.85440807609057198785469717500136190134967176618860803340696566101393777502846
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 1089899043 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x49244f04) == 0x1
        UVM_INFO @ 1089899043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.946733314565335753633157784616117886943419463389079507455299313811342184370
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 668705449 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe5f95d04) == 0x1
        UVM_INFO @ 668705449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.97936363507876965647752145080966402910018186789548033986887421648790029172734
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 257115042 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 257115042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---