SPI_DEVICE/2P Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	54.290s	0.000us	2	2	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	0.000us	2	2	100.00
V1	csr_rw	spi_device_csr_rw	2.060s	0.000us	2	2	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.170s	0.000us	2	2	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.850s	0.000us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.690s	0.000us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.060s	0.000us	2	2	100.00
		spi_device_csr_aliasing	14.850s	0.000us	2	2	100.00
V1	mem_walk	spi_device_mem_walk	0.800s	0.000us	2	2	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.720s	0.000us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	csb_read	spi_device_csb_read	0.890s	0.000us	2	2	100.00
V2	mem_parity	spi_device_mem_parity	0.850s	0.000us	1	2	50.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	0.000us	1	2	50.00
V2	tpm_read	spi_device_tpm_rw	1.080s	0.000us	2	2	100.00
V2	tpm_write	spi_device_tpm_rw	1.080s	0.000us	2	2	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	14.030s	0.000us	2	2	100.00
		spi_device_tpm_sts_read	0.800s	0.000us	2	2	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.180s	0.000us	2	2	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.900s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.910s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.910s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_info_slots	spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_read_status	spi_device_intercept	2.760s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_read_jedec	spi_device_intercept	2.760s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.760s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_fast_read	spi_device_intercept	2.760s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.760s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	flash_cmd_upload	spi_device_upload	6.330s	0.000us	2	2	100.00
V2	mailbox_command	spi_device_mailbox	12.790s	0.000us	2	2	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.790s	0.000us	2	2	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.790s	0.000us	2	2	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.240s	0.000us	2	2	100.00
		spi_device_read_buffer_direct	5.640s	0.000us	2	2	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.790s	0.000us	2	2	100.00
		spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	quad_spi	spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	dual_spi	spi_device_flash_all	24.580s	0.000us	2	2	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.950s	0.000us	2	2	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.950s	0.000us	2	2	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	54.290s	0.000us	2	2	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	114.910s	0.000us	2	2	100.00
V2	stress_all	spi_device_stress_all	123.890s	0.000us	2	2	100.00
V2	alert_test	spi_device_alert_test	0.710s	0.000us	2	2	100.00
V2	intr_test	spi_device_intr_test	0.740s	0.000us	2	2	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.420s	0.000us	2	2	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.420s	0.000us	2	2	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	0.000us	2	2	100.00
		spi_device_csr_rw	2.060s	0.000us	2	2	100.00
		spi_device_csr_aliasing	14.850s	0.000us	2	2	100.00
		spi_device_same_csr_outstanding	2.900s	0.000us	2	2	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	0.000us	2	2	100.00
		spi_device_csr_rw	2.060s	0.000us	2	2	100.00
		spi_device_csr_aliasing	14.850s	0.000us	2	2	100.00
		spi_device_same_csr_outstanding	2.900s	0.000us	2	2	100.00
V2		TOTAL			42	44	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.010s	0.000us	2	2	100.00
		spi_device_tl_intg_err	9.870s	0.000us	2	2	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.870s	0.000us	2	2	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	19.590s	0.000us	2	2	100.00
		TOTAL			64	66	96.97

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.14	99.16	95.76	87.74	89.36	98.44	94.27	73.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.7844692883034503152513016379636419371307476234927389275909623175748775927066
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2608532 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[48])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2608532 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2608532 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[944])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.14230169195319434065935898464914924622036690329348437490492218960940470797187
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   7039915 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e0ba2 [111100000101110100010] vs 0x0 [0])
        UVM_ERROR @   7050915 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x69b834 [11010011011100000110100] vs 0x0 [0])
        UVM_ERROR @   7097915 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x94480e [100101000100100000001110] vs 0x0 [0])
        UVM_ERROR @   7111915 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3fb72c [1111111011011100101100] vs 0x0 [0])
        UVM_ERROR @   7183915 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6e6a15 [11011100110101000010101] vs 0x0 [0])