SPI_HOST Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.000s	584.732us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	18.089us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	140.362us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	211.472us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	21.534us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	28.455us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	140.362us	1	1	100.00
		spi_host_csr_aliasing	2.000s	21.534us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.161us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	26.321us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	41.705us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	80.683us	1	1	100.00
		spi_host_error_cmd	1.000s	53.111us	1	1	100.00
		spi_host_event	33.000s	1752.347us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	254.018us	1	1	100.00
V2	speed	spi_host_speed	3.000s	254.018us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	254.018us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	422.986us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	87.890us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	254.018us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	254.018us	1	1	100.00
V2	duplex	spi_host_smoke	8.000s	584.732us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	8.000s	584.732us	1	1	100.00
V2	stress_all	spi_host_stress_all	15.000s	2955.548us	1	1	100.00
V2	spien	spi_host_spien	17.000s	1448.596us	1	1	100.00
V2	stall	spi_host_status_stall	53.000s	7663.419us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	332.103us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	80.683us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	28.019us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	35.712us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	32.091us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	32.091us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	18.089us	1	1	100.00
		spi_host_csr_rw	1.000s	140.362us	1	1	100.00
		spi_host_csr_aliasing	2.000s	21.534us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	17.380us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	18.089us	1	1	100.00
		spi_host_csr_rw	1.000s	140.362us	1	1	100.00
		spi_host_csr_aliasing	2.000s	21.534us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	17.380us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_sec_cm	2.000s	165.179us	1	1	100.00
		spi_host_tl_intg_err	2.000s	329.801us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	329.801us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	195.000s	21912.533us	1	1	100.00
		TOTAL			26	26	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.64	96.64	92.95	98.47	92.51	87.60	100.00	93.54	89.17