SRAM_CTRL/MAIN Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.270s	0.000us	2	2	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	0.000us	2	2	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	0.000us	2	2	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.420s	0.000us	2	2	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	0.000us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.310s	0.000us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.740s	0.000us	2	2	100.00
V1	mem_walk	sram_ctrl_mem_walk	136.380s	0.000us	2	2	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	57.840s	0.000us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	293.910s	0.000us	2	2	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	237.400s	0.000us	2	2	100.00
V2	bijection	sram_ctrl_bijection	636.980s	0.000us	2	2	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1038.080s	0.000us	2	2	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	33.010s	0.000us	2	2	100.00
V2	executable	sram_ctrl_executable	899.000s	0.000us	2	2	100.00
V2	partial_access	sram_ctrl_partial_access	61.190s	0.000us	2	2	100.00
		sram_ctrl_partial_access_b2b	267.260s	0.000us	2	2	100.00
V2	max_throughput	sram_ctrl_max_throughput	37.060s	0.000us	2	2	100.00
		sram_ctrl_throughput_w_partial_write	18.520s	0.000us	2	2	100.00
		sram_ctrl_throughput_w_readback	56.700s	0.000us	2	2	100.00
V2	regwen	sram_ctrl_regwen	1013.980s	0.000us	2	2	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.340s	0.000us	2	2	100.00
V2	stress_all	sram_ctrl_stress_all	3869.290s	0.000us	2	2	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	0.000us	2	2	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.140s	0.000us	2	2	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.140s	0.000us	2	2	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	0.000us	2	2	100.00
		sram_ctrl_csr_rw	0.700s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.740s	0.000us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.750s	0.000us	2	2	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	0.000us	2	2	100.00
		sram_ctrl_csr_rw	0.700s	0.000us	2	2	100.00
		sram_ctrl_csr_aliasing	0.740s	0.000us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.750s	0.000us	2	2	100.00
V2		TOTAL			34	34	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.900s	0.000us	2	2	100.00
V2S	tl_intg_err	sram_ctrl_tl_intg_err	2.220s	0.000us	2	2	100.00
		sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.220s	0.000us	2	2	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1013.980s	0.000us	2	2	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1013.980s	0.000us	2	2	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	0.000us	2	2	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	899.000s	0.000us	2	2	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	899.000s	0.000us	2	2	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	899.000s	0.000us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	33.010s	0.000us	2	2	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.140s	0.000us	1	2	50.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.900s	0.000us	2	2	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.090s	0.000us	1	2	50.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.270s	0.000us	2	2	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.270s	0.000us	2	2	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	899.000s	0.000us	2	2	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	33.010s	0.000us	2	2	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.270s	0.000us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.790s	0.000us	0	2	0.00
V2S		TOTAL			6	10	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	61.380s	0.000us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			58	62	93.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.89	97.77	91.68	90.71	76.19	95.79	95.55	95.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.16252052664681547126838285101840644957296752282940181255904038824298568195745
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  93044553 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x6c)
        UVM_INFO @  93044553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.65503798073213138417736231244637062116268944262446623030329309612131261888970
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  36487735 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  36487735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103255654418741213974963322849360433547971963072306226261591562995204002198428
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7494124 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7494124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.4829874167791269087569222951430387388170228937383332506988811413780370940358
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5275515 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5275515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---