SYSRST_CTRL Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.410s	0.000us	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.870s	0.000us	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.380s	0.000us	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.060s	0.000us	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	1.850s	0.000us	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.380s	0.000us	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	171.980s	0.000us	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	2.800s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.820s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.380s	0.000us	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.800s	0.000us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	186.510s	0.000us	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	150.720s	0.000us	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	6.840s	0.000us	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.980s	0.000us	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.950s	0.000us	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.520s	0.000us	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.800s	0.000us	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	0.860s	0.000us	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.660s	0.000us	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	18.750s	0.000us	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.780s	0.000us	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.830s	0.000us	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.450s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.650s	0.000us	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.650s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	1.850s	0.000us	1	1	100.00
		sysrst_ctrl_csr_rw	1.380s	0.000us	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.800s	0.000us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	15.140s	0.000us	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	1.850s	0.000us	1	1	100.00
		sysrst_ctrl_csr_rw	1.380s	0.000us	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.800s	0.000us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	15.140s	0.000us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	10.950s	0.000us	1	1	100.00
		sysrst_ctrl_tl_intg_err	7.970s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	7.970s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.900s	0.000us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.42	97.26	95.30	100.00	74.36	97.37	93.87	67.75

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.31475201141217224474377888717607946299259495368007839308762770059707295034551
      Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 4284869924 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 4284910739 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 4284910739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---