UART Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: efa7857

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.290s	0.000us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.580s	0.000us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.750s	0.000us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.650s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.710s	0.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.580s	0.000us	1	1	100.00
		uart_csr_aliasing	0.650s	0.000us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	87.460s	0.000us	1	1	100.00
V2	parity	uart_smoke	1.290s	0.000us	1	1	100.00
		uart_tx_rx	87.460s	0.000us	1	1	100.00
V2	parity_error	uart_intr	77.150s	0.000us	1	1	100.00
		uart_rx_parity_err	50.970s	0.000us	1	1	100.00
V2	watermark	uart_tx_rx	87.460s	0.000us	1	1	100.00
		uart_intr	77.150s	0.000us	1	1	100.00
V2	fifo_full	uart_fifo_full	9.430s	0.000us	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	22.350s	0.000us	1	1	100.00
V2	fifo_reset	uart_fifo_reset	5.300s	0.000us	1	1	100.00
V2	rx_frame_err	uart_intr	77.150s	0.000us	1	1	100.00
V2	rx_break_err	uart_intr	77.150s	0.000us	1	1	100.00
V2	rx_timeout	uart_intr	77.150s	0.000us	1	1	100.00
V2	perf	uart_perf	250.160s	0.000us	1	1	100.00
V2	sys_loopback	uart_loopback	4.180s	0.000us	1	1	100.00
V2	line_loopback	uart_loopback	4.180s	0.000us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.510s	0.000us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.250s	0.000us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.610s	0.000us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	7.810s	0.000us	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	251.970s	0.000us	1	1	100.00
V2	stress_all	uart_stress_all	27.370s	0.000us	1	1	100.00
V2	alert_test	uart_alert_test	0.550s	0.000us	1	1	100.00
V2	intr_test	uart_intr_test	0.580s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.350s	0.000us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.350s	0.000us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
		uart_csr_rw	0.580s	0.000us	1	1	100.00
		uart_csr_aliasing	0.650s	0.000us	1	1	100.00
		uart_same_csr_outstanding	0.610s	0.000us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
		uart_csr_rw	0.580s	0.000us	1	1	100.00
		uart_csr_aliasing	0.650s	0.000us	1	1	100.00
		uart_same_csr_outstanding	0.610s	0.000us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.730s	0.000us	1	1	100.00
		uart_tl_intg_err	1.110s	0.000us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.110s	0.000us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.850s	0.000us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.09	99.48	97.78	91.55	--	98.14	97.12	56.47

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.96724301460726271144996894416461938358323738293395306790725463530875873105236
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1862398705 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 1862410199 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 1862513645 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 1899616277 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 1899616277 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0