CHIP Simulation Results

Wednesday November 12 2025 17:51:03 UTC

GitHub Revision: `efa7857`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	118.620s	0.000us	1	1	100.00
		chip_sw_example_rom	73.120s	0.000us	1	1	100.00
		chip_sw_example_manufacturer	140.570s	0.000us	1	1	100.00
		chip_sw_example_concurrency	101.570s	0.000us	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	248.370s	0.000us	1	1	100.00
V1	csr_rw	chip_csr_rw	221.390s	0.000us	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	138.960s	0.000us	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	5286.540s	0.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.900s	0.000us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	5286.540s	0.000us	1	1	100.00
		chip_csr_rw	221.390s	0.000us	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.290s	0.000us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	286.180s	0.000us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	286.180s	0.000us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	286.180s	0.000us	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	386.610s	0.000us	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	386.610s	0.000us	1	1	100.00
		chip_sw_uart_tx_rx_idx1	423.940s	0.000us	1	1	100.00
		chip_sw_uart_tx_rx_idx2	324.330s	0.000us	1	1	100.00
		chip_sw_uart_tx_rx_idx3	357.140s	0.000us	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	329.390s	0.000us	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1781.780s	0.000us	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	701.620s	0.000us	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	142.260s	0.000us	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	142.260s	0.000us	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	174.640s	0.000us	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	169.030s	0.000us	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	157.490s	0.000us	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	96.020s	0.000us	1	1	100.00
		chip_tap_straps_testunlock0	208.380s	0.000us	1	1	100.00
		chip_tap_straps_rma	71.460s	0.000us	1	1	100.00
		chip_tap_straps_prod	108.960s	0.000us	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	134.680s	0.000us	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	844.150s	0.000us	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	416.190s	0.000us	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	416.190s	0.000us	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	669.190s	0.000us	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	2348.850s	0.000us	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	343.080s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	592.060s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3389.090s	0.000us	1	1	100.00
		chip_sw_aes_enc_jitter_en	149.130s	0.000us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	753.320s	0.000us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	137.890s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1365.320s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.380s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	382.780s	0.000us	1	1	100.00
		chip_sw_clkmgr_jitter	133.730s	0.000us	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	215.930s	0.000us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	298.290s	0.000us	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	265.030s	0.000us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	135.670s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	265.030s	0.000us	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	118.790s	0.000us	1	1	100.00
		chip_sw_aes_smoketest	145.290s	0.000us	1	1	100.00
		chip_sw_aon_timer_smoketest	152.540s	0.000us	1	1	100.00
		chip_sw_clkmgr_smoketest	154.930s	0.000us	1	1	100.00
		chip_sw_csrng_smoketest	129.250s	0.000us	1	1	100.00
		chip_sw_entropy_src_smoketest	743.400s	0.000us	1	1	100.00
		chip_sw_gpio_smoketest	133.760s	0.000us	1	1	100.00
		chip_sw_hmac_smoketest	199.770s	0.000us	1	1	100.00
		chip_sw_kmac_smoketest	209.210s	0.000us	1	1	100.00
		chip_sw_otbn_smoketest	739.790s	0.000us	1	1	100.00
		chip_sw_pwrmgr_smoketest	206.420s	0.000us	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	290.320s	0.000us	1	1	100.00
		chip_sw_rv_plic_smoketest	125.710s	0.000us	1	1	100.00
		chip_sw_rv_timer_smoketest	145.600s	0.000us	1	1	100.00
		chip_sw_rstmgr_smoketest	133.110s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	149.070s	0.000us	1	1	100.00
		chip_sw_uart_smoketest	140.640s	0.000us	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	134.480s	0.000us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	295.470s	0.000us	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	8012.980s	0.000us	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2527.600s	0.000us	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	750.900s	0.000us	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	216.570s	0.000us	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	238.930s	0.000us	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	6993.820s	0.000us	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	7582.010s	0.000us	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	55.180s	0.000us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	55.180s	0.000us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	5286.540s	0.000us	1	1	100.00
		chip_same_csr_outstanding	1333.580s	0.000us	1	1	100.00
		chip_csr_hw_reset	248.370s	0.000us	1	1	100.00
		chip_csr_rw	221.390s	0.000us	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	5286.540s	0.000us	1	1	100.00
		chip_same_csr_outstanding	1333.580s	0.000us	1	1	100.00
		chip_csr_hw_reset	248.370s	0.000us	1	1	100.00
		chip_csr_rw	221.390s	0.000us	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.860s	0.000us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.550s	0.000us	1	1	100.00
		xbar_smoke_large_delays	57.280s	0.000us	1	1	100.00
		xbar_smoke_slow_rsp	43.750s	0.000us	1	1	100.00
		xbar_random_zero_delays	34.140s	0.000us	1	1	100.00
		xbar_random_large_delays	33.320s	0.000us	1	1	100.00
		xbar_random_slow_rsp	205.750s	0.000us	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.360s	0.000us	1	1	100.00
		xbar_error_and_unmapped_addr	11.620s	0.000us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	37.240s	0.000us	1	1	100.00
		xbar_error_and_unmapped_addr	11.620s	0.000us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	10.040s	0.000us	1	1	100.00
		xbar_access_same_device_slow_rsp	607.720s	0.000us	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	6.140s	0.000us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	125.280s	0.000us	1	1	100.00
		xbar_stress_all_with_error	143.360s	0.000us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	137.340s	0.000us	1	1	100.00
		xbar_stress_all_with_reset_error	27.390s	0.000us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	2527.600s	0.000us	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	2311.720s	0.000us	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2395.820s	0.000us	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	1992.060s	0.000us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2732.340s	0.000us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2623.620s	0.000us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2570.800s	0.000us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2563.560s	0.000us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.250s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.060s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.930s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.020s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.300s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	19.130s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.190s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.970s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	20.160s	0.000us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.790s	0.000us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.640s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.700s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.950s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.780s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	19.920s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.710s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.150s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	21.050s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.170s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.660s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.050s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.260s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.100s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.200s	0.000us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.830s	0.000us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1963.480s	0.000us	1	1	100.00
		rom_e2e_asm_init_dev	2431.690s	0.000us	1	1	100.00
		rom_e2e_asm_init_prod	2590.410s	0.000us	1	1	100.00
		rom_e2e_asm_init_prod_end	2430.990s	0.000us	1	1	100.00
		rom_e2e_asm_init_rma	2424.480s	0.000us	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2344.330s	0.000us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2367.820s	0.000us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2323.870s	0.000us	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2564.100s	0.000us	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3231.300s	0.000us	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3231.300s	0.000us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	151.570s	0.000us	1	1	100.00
		chip_sw_aes_enc_jitter_en	149.130s	0.000us	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	149.160s	0.000us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	201.820s	0.000us	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	998.920s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	133.470s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	343.580s	0.000us	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	534.140s	0.000us	1	1	100.00
		chip_plic_all_irqs_10	307.780s	0.000us	1	1	100.00
		chip_plic_all_irqs_20	307.300s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	166.110s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	852.040s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	169.340s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	103.370s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	995.720s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	1237.900s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	812.380s	0.000us	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7184.840s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	247.950s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	206.420s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	247.950s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	389.420s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	389.420s	0.000us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	262.530s	0.000us	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	321.280s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	591.700s	0.000us	1	1	100.00
		chip_sw_aes_idle	201.820s	0.000us	1	1	100.00
		chip_sw_hmac_enc_idle	200.170s	0.000us	1	1	100.00
		chip_sw_kmac_idle	104.990s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	259.750s	0.000us	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	202.800s	0.000us	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	251.220s	0.000us	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	309.990s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	836.270s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	339.660s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	395.080s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	378.200s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	352.830s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	418.830s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	368.410s	0.000us	1	1	100.00
		chip_sw_ast_clk_outputs	669.190s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	308.770s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	378.200s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	352.830s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	343.080s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	592.060s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3389.090s	0.000us	1	1	100.00
		chip_sw_aes_enc_jitter_en	149.130s	0.000us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	753.320s	0.000us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	137.890s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1365.320s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.380s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	382.780s	0.000us	1	1	100.00
		chip_sw_clkmgr_jitter	133.730s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	122.670s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	401.570s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	708.320s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	2958.670s	0.000us	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	132.850s	0.000us	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	128.850s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1284.220s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	167.550s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	375.160s	0.000us	1	1	100.00
		chip_sw_flash_init_reduced_freq	998.740s	0.000us	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11522.220s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	669.190s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	392.760s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	201.660s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	995.720s	0.000us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	784.790s	0.000us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	145.060s	0.000us	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	374.780s	0.000us	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	203.740s	0.000us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	3868.330s	0.000us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	173.020s	0.000us	1	1	100.00
		chip_sw_edn_entropy_reqs	720.590s	0.000us	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	173.020s	0.000us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	784.790s	0.000us	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	178.420s	0.000us	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1009.540s	0.000us	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	557.680s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	592.060s	0.000us	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	331.250s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	343.080s	0.000us	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	3769.180s	0.000us	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1009.540s	0.000us	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	207.450s	0.000us	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	3769.180s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	220.210s	0.000us	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	514.550s	0.000us	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	363.810s	0.000us	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	363.810s	0.000us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	123.820s	0.000us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	137.890s	0.000us	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	200.170s	0.000us	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1090.090s	0.000us	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	299.090s	0.000us	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	445.070s	0.000us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	407.770s	0.000us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	368.510s	0.000us	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	253.680s	0.000us	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1365.320s	0.000us	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	1363.010s	0.000us	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	998.920s	0.000us	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2543.600s	0.000us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	145.900s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac	186.720s	0.000us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	179.380s	0.000us	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	161.420s	0.000us	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	944.620s	0.000us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	104.990s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	343.580s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	96.020s	0.000us	1	1	100.00
		chip_tap_straps_rma	71.460s	0.000us	1	1	100.00
		chip_tap_straps_prod	108.960s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	171.800s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	1313.340s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	220.210s	0.000us	1	1	100.00
		chip_rv_dm_lc_disabled	324.480s	0.000us	1	1	100.00
		chip_sw_flash_ctrl_lc_rw_en	214.020s	0.000us	1	1	100.00
		chip_sw_flash_rma_unlocked	3769.180s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	199.210s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	478.040s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	473.930s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	413.470s	0.000us	0	1	0.00
		chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	355.540s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_execution_main	477.490s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	308.770s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	339.660s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	395.080s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	378.200s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	352.830s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	418.830s	0.000us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	368.410s	0.000us	1	1	100.00
		chip_tap_straps_dev	96.020s	0.000us	1	1	100.00
		chip_tap_straps_rma	71.460s	0.000us	1	1	100.00
		chip_tap_straps_prod	108.960s	0.000us	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	113.020s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	74.860s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	85.340s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	103.040s	0.000us	1	1	100.00
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	324.480s	0.000us	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1325.470s	0.000us	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3892.700s	0.000us	1	1	100.00
		chip_sw_lc_walkthrough_prod	4230.740s	0.000us	1	1	100.00
		chip_sw_lc_walkthrough_prodend	592.850s	0.000us	1	1	100.00
		chip_sw_lc_walkthrough_rma	3847.200s	0.000us	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1325.470s	0.000us	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	66.620s	0.000us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	65.530s	0.000us	1	1	100.00
		rom_volatile_raw_unlock	52.980s	0.000us	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3294.620s	0.000us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3389.090s	0.000us	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	591.700s	0.000us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	591.700s	0.000us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	591.700s	0.000us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	285.240s	0.000us	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1009.540s	0.000us	1	1	100.00
		chip_sw_otbn_mem_scramble	285.240s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	390.290s	0.000us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	115.880s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1009.540s	0.000us	1	1	100.00
		chip_sw_otbn_mem_scramble	285.240s	0.000us	1	1	100.00
		chip_sw_keymgr_key_derivation	1590.710s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	390.290s	0.000us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	115.880s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	262.740s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	171.800s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	220.210s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	199.210s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	478.040s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	473.930s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	413.470s	0.000us	0	1	0.00
		chip_sw_lc_ctrl_transition	392.360s	0.000us	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	220.210s	0.000us	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1152.510s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	304.200s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	1235.020s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	191.880s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	384.080s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	276.040s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	934.370s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	377.910s	0.000us	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	389.420s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	834.870s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	261.090s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	304.200s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	240.910s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1436.390s	0.000us	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	364.680s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	364.210s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1507.750s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	598.290s	0.000us	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	993.990s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1753.560s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	143.570s	0.000us	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	355.540s	0.000us	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	355.540s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	993.990s	0.000us	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1507.750s	0.000us	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	261.090s	0.000us	1	1	100.00
		chip_sw_pwrmgr_smoketest	206.420s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	291.510s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	176.210s	0.000us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	187.640s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	852.040s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	156.550s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	1237.900s	0.000us	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	456.180s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	479.640s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	146.620s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	115.880s	0.000us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	176.210s	0.000us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	176.210s	0.000us	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	891.390s	0.000us	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	867.110s	0.000us	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	291.510s	0.000us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	358.810s	0.000us	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	204.860s	0.000us	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	71.460s	0.000us	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	324.480s	0.000us	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	534.140s	0.000us	1	1	100.00
		chip_plic_all_irqs_10	307.780s	0.000us	1	1	100.00
		chip_plic_all_irqs_20	307.300s	0.000us	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	150.340s	0.000us	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	177.940s	0.000us	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2527.600s	0.000us	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	486.590s	0.000us	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	190.070s	0.000us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	235.350s	0.000us	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	149.570s	0.000us	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	390.290s	0.000us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	382.780s	0.000us	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	344.060s	0.000us	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	473.910s	0.000us	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	477.490s	0.000us	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
		chip_sw_data_integrity_escalation	416.190s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	598.290s	0.000us	1	1	100.00
		chip_sw_sysrst_ctrl_reset	1038.140s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	139.980s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	196.600s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	335.830s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	1038.140s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	1038.140s	0.000us	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	760.640s	0.000us	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	760.640s	0.000us	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	286.890s	0.000us	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3231.300s	0.000us	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	97.410s	0.000us	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	183.960s	0.000us	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	284.220s	0.000us	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	276.340s	0.000us	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	1115.480s	0.000us	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	5221.770s	0.000us	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1860.450s	0.000us	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	138.940s	0.000us	1	1	100.00
V2		TOTAL			233	275	84.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	147.720s	0.000us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	165.220s	0.000us	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	9279.270s	0.000us	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1035.130s	0.000us	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1175.660s	0.000us	1	1	100.00
		rom_e2e_jtag_debug_dev	1190.580s	0.000us	1	1	100.00
		rom_e2e_jtag_debug_rma	483.940s	0.000us	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	244.010s	0.000us	1	1	100.00
		rom_e2e_jtag_inject_dev	230.160s	0.000us	1	1	100.00
		rom_e2e_jtag_inject_rma	224.340s	0.000us	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.838s	0.000us	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	572.980s	0.000us	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	296.490s	0.000us	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	923.230s	0.000us	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	942.370s	0.000us	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	217.920s	0.000us	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	620.250s	0.000us	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	61.920s	0.000us	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	183.460s	0.000us	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	251.100s	0.000us	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	300.860s	0.000us	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	993.990s	0.000us	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1175.660s	0.000us	1	1	100.00
		rom_e2e_jtag_debug_dev	1190.580s	0.000us	1	1	100.00
		rom_e2e_jtag_debug_rma	483.940s	0.000us	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	322.540s	0.000us	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	278.090s	0.000us	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	5378.880s	0.000us	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	5378.880s	0.000us	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	152.280s	0.000us	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	386.610s	0.000us	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	2995.500s	0.000us	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	175.640s	0.000us	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	351.350s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	2034.350s	0.000us	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	126.870s	0.000us	1	1	100.00
		chip_sw_otp_ctrl_descrambling	193.640s	0.000us	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	202.510s	0.000us	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.973s	0.000us	0	1	0.00
		chip_sw_flash_ctrl_write_clear	176.300s	0.000us	1	1	100.00
		TOTAL			276	326	84.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.51	94.46	89.32	91.38	57.14	93.85	96.28	41.12

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.31410111877884501345645811528273892785121094132770541567889580599326303912994
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.73023258322771838543032191306302622665322288425176553268004421173320445781073
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.77840623132554348655108515210868572515530957714556979468776408140759117980408
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.85344656114187023886991883897601996944798196310995656912160726849959303692073
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.85054156534999012524182587041980055402861296962337017299218001577513325899027
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.56790742183455068493599572553556166966201302177807191346934289632268444746431
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.47264040839280994213562583848372546948944195657166096386995514738801838964637
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3827744984530987890374990921213300724002473346808241297352302171626310262454
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.32203361262241857254964487129670254004470787080908818217971048300914272112516
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.113007423400244391927079809202960655145163584476292378176684552337541300702655
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.55606730223797630735681803327403887299534397195873516789161851645921288471036
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 10211.440000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 10211.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.31548378181530376568138510096836580886658740845173469488487219702978152708566
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 26048.661000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 26048.661000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.56699213847385150651292174851867890239675935816270497303068359105764624548295
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7885.762500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7885.762500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.58246205311112270456072331690531275987624811129438809932878146082691773542337
    Line 525, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.95350817015478987669810580189617093239370978446715064374920822785169705307859
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.12149475664644041293435274384141768094491678078989061087077662284264597217893
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.72203636478829970194047780591671645910225928535924951196430596293698669003764
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2561.989546 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2561.989546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.113167005312053602127562951930915159565362484895760554317979014121372222089954
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3112.594256 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3112.594256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.71661012494369985113690310212645461444083042805683515803898495329712104248724
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.163s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.109227033830226087906581097894737405486868798589225956204113042385177370407484
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.114086967913941647491725916045028731682711891177947001423330036313399780238024
    Line 549, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.42636346803644609916732869446212048902001008838216212096975290526915287230279
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.17372719433729016738985294246684186659448634656741698393901774429907295126766
    Line 544, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.39161235296609240791858355258035037317122763227863696028859427626825966059857
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34009) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.58084461867308921168596875729569544359898511892101829620224830878601022245696
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2308.790880 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34009) { a_addr: 'h10414  a_data: 'h78a24922  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1bdeb  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2308.790880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32117) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.103410087415512992805113540673090232982192593312932251974581946500834133555886
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1777.827689 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32117) { a_addr: 'h10434  a_data: 'h81e33559  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h4  a_user: 'h1a57e  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1777.827689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.103187760450234480399095950450479784943820852880810062437575575658953979891796
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2689.013645 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.84144541297664201255893827119804968364931157523823894748009087180665687423315
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7195.227128 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7195.227128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.38340958143200165058562025747567426006265143709977466455887340739144001275993
    Line 452, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 33724.711248 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 33724.711248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78269) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.63004133912105069828143221594555474108447334766109859997022547717560123470583
Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4125.124982 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78269) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4125.124982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.9547719690005630578606580851775399964105610858224422432729586486929858816475
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11823.793031 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11823.793031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.104458473467198670173489887461857627073576403468114932674577862799866357224202
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34443.317011 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34443.317011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.113586068764527269738255278674550724561199264139011387141778475464656454132695
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3331.762861 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3331.762861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.82903268034037099170877802733257788165616218803126663348814340200215528103595
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2568.788678 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2568.788678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.62226381357815026092184013549118669430854037727337364001407129299337689534234
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.111697293136894113050786504235734082478105274902929351574160794387616482835720
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3674.143180 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3674.143180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.63557365847673152146464087695826698810497411389916919009549502610163365870701
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2569.968784 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2569.968784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.63680925034641717124915463274857352558516406479648378704809637325993526233539
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3422.257000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3422.257000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.68533305398894469750283113298335781956209450864185523363174372045158096353624
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3682.093500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3682.093500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.103841877482114996830103281430080695097901537298199097679583318388974101332057
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22054.504294 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22054.504294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.13303728590240892577399642462163806273357512463503674730003356662320704242882
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.103053331335193826804487324596107003363962922757431946988778148413153701908259
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.64139261722755351360024835625579616968296502922585088624841120677488249601641
    Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 13882.485607 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13882.485607 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.43787722186976883458319209742036135204810446116073746682586668755791458387416
    Line 430, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 16033.481791 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 16033.481791 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```