ADC_CTRL Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.280s	5816.680us	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	0.920s	1214.780us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.890s	539.753us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	97.600s	44196.947us	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.470s	1155.078us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.300s	493.543us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.890s	539.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	1155.078us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	65.570s	159354.570us	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	815.580s	490028.696us	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	63.930s	158869.526us	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	197.440s	484264.797us	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	135.600s	181849.630us	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	162.910s	407745.903us	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	204.290s	496782.615us	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	541.850s	2000000.000us	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.200s	3569.584us	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	49.300s	27614.025us	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	97.750s	108130.070us	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	351.670s	386150.504us	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.880s	544.091us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.220s	308.202us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.900s	410.566us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.900s	410.566us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	0.920s	1214.780us	1	1	100.00
		adc_ctrl_csr_rw	0.890s	539.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	1155.078us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.230s	1523.789us	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	0.920s	1214.780us	1	1	100.00
		adc_ctrl_csr_rw	0.890s	539.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.470s	1155.078us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.230s	1523.789us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.160s	4236.954us	1	1	100.00
		adc_ctrl_tl_intg_err	16.560s	8326.883us	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.560s	8326.883us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	64.770s	317809.815us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			23	25	92.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.05	99.02	95.37	100.00	97.30	98.58	95.46	37.60

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.61301403216903275629495413655572724559086202770912515224995172943639703482158
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.112474175623954029989856388343982732937363583272849883129568414089557317898567
      Line 207, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 317809814641 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 317809814641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---