| V1 |
smoke |
aon_timer_smoke |
0.860s |
681.849us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
0.770s |
583.820us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.930s |
429.215us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
7.580s |
7013.458us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.030s |
600.091us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
0.760s |
331.001us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.930s |
429.215us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.030s |
600.091us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.970s |
296.191us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
1.180s |
374.425us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
25.300s |
57977.435us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
0.840s |
532.548us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
23.450s |
69849.731us |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.970s |
524.960us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
1.160s |
331.240us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.240s |
902.695us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.240s |
902.695us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
0.770s |
583.820us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.930s |
429.215us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.030s |
600.091us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.960s |
1182.668us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
0.770s |
583.820us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.930s |
429.215us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.030s |
600.091us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.960s |
1182.668us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
7.070s |
8271.585us |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
11.800s |
8506.275us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
11.800s |
8506.275us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.810s |
529.530us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.440s |
467.114us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
2.610s |
4306.661us |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
1.390s |
552.258us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
3.090s |
4160.047us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
14.490s |
9673.017us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |