EDN Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.850s	57.231us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.080s	18.250us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.840s	12.192us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.520s	522.407us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.900s	94.980us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.180s	73.483us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.840s	12.192us	1	1	100.00
		edn_csr_aliasing	0.900s	94.980us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.710s	291.583us	1	1	100.00
V2	csrng_commands	edn_genbits	1.710s	291.583us	1	1	100.00
V2	genbits	edn_genbits	1.710s	291.583us	1	1	100.00
V2	interrupts	edn_intr	0.900s	32.554us	1	1	100.00
V2	alerts	edn_alert	1.030s	39.221us	1	1	100.00
V2	errs	edn_err	1.070s	40.311us	1	1	100.00
V2	disable	edn_disable	0.880s	13.246us	1	1	100.00
		edn_disable_auto_req_mode	1.080s	44.310us	1	1	100.00
V2	stress_all	edn_stress_all	3.380s	1133.638us	1	1	100.00
V2	intr_test	edn_intr_test	0.830s	17.314us	1	1	100.00
V2	alert_test	edn_alert_test	1.100s	45.274us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.480s	206.306us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.480s	206.306us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.080s	18.250us	1	1	100.00
		edn_csr_rw	0.840s	12.192us	1	1	100.00
		edn_csr_aliasing	0.900s	94.980us	1	1	100.00
		edn_same_csr_outstanding	1.070s	48.444us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.080s	18.250us	1	1	100.00
		edn_csr_rw	0.840s	12.192us	1	1	100.00
		edn_csr_aliasing	0.900s	94.980us	1	1	100.00
		edn_same_csr_outstanding	1.070s	48.444us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_tl_intg_err	3.440s	215.169us	1	1	100.00
		edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.820s	30.851us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.030s	39.221us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.030s	39.221us	1	1	100.00
		edn_sec_cm	5.540s	915.975us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.030s	39.221us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.440s	215.169us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.110s	2484.443us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.20	98.25	88.52	86.10	53.49	94.13	96.89	79.01