HMAC Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	3.880s	698.005us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.920s	109.508us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.820s	222.132us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	3.890s	220.558us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	3.980s	111.076us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	2.140s	173.807us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.820s	222.132us	1	1	100.00
		hmac_csr_aliasing	3.980s	111.076us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	64.440s	17708.729us	1	1	100.00
V2	back_pressure	hmac_back_pressure	23.340s	2704.606us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	176.470s	5552.513us	1	1	100.00
		hmac_test_sha384_vectors	359.880s	32829.698us	1	1	100.00
		hmac_test_sha512_vectors	19.750s	454.620us	1	1	100.00
		hmac_test_hmac256_vectors	13.410s	611.763us	1	1	100.00
		hmac_test_hmac384_vectors	9.200s	557.640us	1	1	100.00
		hmac_test_hmac512_vectors	8.680s	1072.401us	1	1	100.00
V2	burst_wr	hmac_burst_wr	23.130s	2399.187us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	164.240s	5863.523us	1	1	100.00
V2	error	hmac_error	72.260s	10768.150us	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	84.660s	5602.912us	1	1	100.00
V2	save_and_restore	hmac_smoke	3.880s	698.005us	1	1	100.00
		hmac_long_msg	64.440s	17708.729us	1	1	100.00
		hmac_back_pressure	23.340s	2704.606us	1	1	100.00
		hmac_datapath_stress	164.240s	5863.523us	1	1	100.00
		hmac_burst_wr	23.130s	2399.187us	1	1	100.00
		hmac_stress_all	1183.130s	9144.343us	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	3.880s	698.005us	1	1	100.00
		hmac_long_msg	64.440s	17708.729us	1	1	100.00
		hmac_back_pressure	23.340s	2704.606us	1	1	100.00
		hmac_datapath_stress	164.240s	5863.523us	1	1	100.00
		hmac_wipe_secret	84.660s	5602.912us	1	1	100.00
		hmac_test_sha256_vectors	176.470s	5552.513us	1	1	100.00
		hmac_test_sha384_vectors	359.880s	32829.698us	1	1	100.00
		hmac_test_sha512_vectors	19.750s	454.620us	1	1	100.00
		hmac_test_hmac256_vectors	13.410s	611.763us	1	1	100.00
		hmac_test_hmac384_vectors	9.200s	557.640us	1	1	100.00
		hmac_test_hmac512_vectors	8.680s	1072.401us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	3.880s	698.005us	1	1	100.00
		hmac_long_msg	64.440s	17708.729us	1	1	100.00
		hmac_back_pressure	23.340s	2704.606us	1	1	100.00
		hmac_datapath_stress	164.240s	5863.523us	1	1	100.00
		hmac_burst_wr	23.130s	2399.187us	1	1	100.00
		hmac_error	72.260s	10768.150us	1	1	100.00
		hmac_wipe_secret	84.660s	5602.912us	1	1	100.00
		hmac_test_sha256_vectors	176.470s	5552.513us	1	1	100.00
		hmac_test_sha384_vectors	359.880s	32829.698us	1	1	100.00
		hmac_test_sha512_vectors	19.750s	454.620us	1	1	100.00
		hmac_test_hmac256_vectors	13.410s	611.763us	1	1	100.00
		hmac_test_hmac384_vectors	9.200s	557.640us	1	1	100.00
		hmac_test_hmac512_vectors	8.680s	1072.401us	1	1	100.00
		hmac_stress_all	1183.130s	9144.343us	1	1	100.00
V2	stress_all	hmac_stress_all	1183.130s	9144.343us	1	1	100.00
V2	alert_test	hmac_alert_test	0.740s	14.935us	1	1	100.00
V2	intr_test	hmac_intr_test	0.850s	40.272us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.680s	68.306us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.680s	68.306us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.920s	109.508us	1	1	100.00
		hmac_csr_rw	0.820s	222.132us	1	1	100.00
		hmac_csr_aliasing	3.980s	111.076us	1	1	100.00
		hmac_same_csr_outstanding	1.580s	85.567us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.920s	109.508us	1	1	100.00
		hmac_csr_rw	0.820s	222.132us	1	1	100.00
		hmac_csr_aliasing	3.980s	111.076us	1	1	100.00
		hmac_same_csr_outstanding	1.580s	85.567us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	1.280s	130.589us	1	1	100.00
		hmac_tl_intg_err	2.030s	809.895us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.030s	809.895us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	3.880s	698.005us	1	1	100.00
V3	stress_reset	hmac_stress_reset	1.190s	84.191us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	198.280s	52836.792us	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	0.980s	14.966us	1	1	100.00
		TOTAL			28	28	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.74	99.79	96.51	100.00	97.06	99.67	96.42	45.73