I2C Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	67.850s	2397.113us	1	1	100.00
V1	target_smoke	i2c_target_smoke	4.730s	1018.286us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.800s	31.804us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.710s	19.645us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.570s	221.457us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.350s	27.017us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.920s	90.663us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.710s	19.645us	1	1	100.00
		i2c_csr_aliasing	1.350s	27.017us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.670s	291.598us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	42.070s	1405.429us	0	1	0.00
V2	host_maxperf	i2c_host_perf	964.200s	50050.692us	1	1	100.00
V2	host_override	i2c_host_override	0.790s	26.485us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	41.260s	5185.491us	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	54.870s	2828.487us	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.080s	110.857us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.960s	285.560us	1	1	100.00
		i2c_host_fifo_reset_rx	3.700s	194.210us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	53.650s	6042.069us	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.510s	996.690us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.360s	583.514us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.940s	2894.696us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1298.020s	66105.366us	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.220s	415.115us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	4.960s	713.417us	1	1	100.00
		i2c_target_intr_smoke	4.220s	3285.801us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.240s	479.288us	1	1	100.00
		i2c_target_fifo_reset_tx	1.450s	488.506us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	853.040s	57030.773us	1	1	100.00
		i2c_target_stress_rd	4.960s	713.417us	1	1	100.00
		i2c_target_intr_stress_wr	8.040s	11377.846us	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.610s	4811.994us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	43.290s	1545.765us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.640s	6039.330us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.030s	1163.269us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.000s	1698.914us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.390s	241.035us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	964.200s	50050.692us	1	1	100.00
		i2c_host_perf_precise	4.990s	148.766us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.510s	996.690us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.800s	319.352us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.120s	559.627us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.840s	452.321us	1	1	100.00
		i2c_target_nack_txstretch	1.160s	513.683us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.770s	1276.855us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.220s	1310.877us	1	1	100.00
V2	alert_test	i2c_alert_test	0.640s	17.629us	1	1	100.00
V2	intr_test	i2c_intr_test	0.760s	16.462us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.930s	45.472us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.930s	45.472us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.800s	31.804us	1	1	100.00
		i2c_csr_rw	0.710s	19.645us	1	1	100.00
		i2c_csr_aliasing	1.350s	27.017us	1	1	100.00
		i2c_same_csr_outstanding	1.090s	64.363us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.800s	31.804us	1	1	100.00
		i2c_csr_rw	0.710s	19.645us	1	1	100.00
		i2c_csr_aliasing	1.350s	27.017us	1	1	100.00
		i2c_same_csr_outstanding	1.090s	64.363us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.370s	222.770us	1	1	100.00
		i2c_sec_cm	1.000s	73.087us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.370s	222.770us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.000s	137.952us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.740s	3140.320us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.220s	1604.093us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.34	96.41	85.12	89.45	44.05	92.33	96.19	79.81

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.92218048396013389058561943086041150050402847672553457997550392966528922376964
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 291598358 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 291598358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.81752426572654299721409309266387477668816987972039438192788911327645249151596
      Line 113, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 1405428618 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1405428618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.103805089316538934912875449583592296831375668033503532566947178877566958777137
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2894696186 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2894696186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.27856073242801548393896017512362910113679449631020976420531397940677872781481
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 3140320031 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 122 [0x7a])
        UVM_INFO @ 3140320031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.94748928921465553059230458425598804700379494957556562100553792503819134757719
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 137952060 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 137952060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.65906992368529387744554329282127053366343606131659136691781080078200326480094
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1604092642 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1604092642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.115527657036320852917663127887791676535346401267265512850444349778526479402354
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 583514457 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------