KEYMGR Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.340s 82.745us 1 1 100.00
V1 random keymgr_random 13.480s 3163.804us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.910s 119.137us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.030s 54.867us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 7.980s 345.798us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 11.010s 516.198us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.120s 16.196us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.030s 54.867us 1 1 100.00
keymgr_csr_aliasing 11.010s 516.198us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 6.590s 192.917us 1 1 100.00
V2 sideload keymgr_sideload 1.500s 184.749us 1 1 100.00
keymgr_sideload_kmac 1.830s 32.772us 1 1 100.00
keymgr_sideload_aes 3.320s 142.114us 1 1 100.00
keymgr_sideload_otbn 1.770s 62.971us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 2.500s 250.132us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.930s 58.430us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.650s 368.742us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.850s 282.972us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.770s 27.589us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.560s 184.186us 1 1 100.00
V2 stress_all keymgr_stress_all 133.210s 19982.659us 1 1 100.00
V2 intr_test keymgr_intr_test 0.990s 12.012us 1 1 100.00
V2 alert_test keymgr_alert_test 0.800s 48.776us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.480s 221.039us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.480s 221.039us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.910s 119.137us 1 1 100.00
keymgr_csr_rw 1.030s 54.867us 1 1 100.00
keymgr_csr_aliasing 11.010s 516.198us 1 1 100.00
keymgr_same_csr_outstanding 1.310s 22.417us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.910s 119.137us 1 1 100.00
keymgr_csr_rw 1.030s 54.867us 1 1 100.00
keymgr_csr_aliasing 11.010s 516.198us 1 1 100.00
keymgr_same_csr_outstanding 1.310s 22.417us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
keymgr_tl_intg_err 2.270s 55.397us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.990s 113.038us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.990s 113.038us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.990s 113.038us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.990s 113.038us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 4.080s 263.465us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.270s 55.397us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.990s 113.038us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 6.590s 192.917us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 13.480s 3163.804us 1 1 100.00
keymgr_csr_rw 1.030s 54.867us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 13.480s 3163.804us 1 1 100.00
keymgr_csr_rw 1.030s 54.867us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 13.480s 3163.804us 1 1 100.00
keymgr_csr_rw 1.030s 54.867us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.930s 58.430us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.770s 27.589us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.770s 27.589us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 13.480s 3163.804us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.260s 86.497us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.350s 54.675us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.930s 58.430us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.350s 54.675us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.350s 54.675us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.350s 54.675us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 3.980s 1106.602us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.350s 54.675us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 8.040s 311.716us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.25 98.70 92.62 96.70 86.05 96.33 97.48 63.88