KMAC/MASKED Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.150s	3223.187us	2	2	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.950s	29.640us	2	2	100.00
V1	csr_rw	kmac_csr_rw	1.020s	36.190us	2	2	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.030s	533.450us	2	2	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.300s	81.104us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.000s	332.041us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.020s	36.190us	2	2	100.00
		kmac_csr_aliasing	3.300s	81.104us	2	2	100.00
V1	mem_walk	kmac_mem_walk	0.780s	115.361us	2	2	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	140.164us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1144.680s	170154.008us	2	2	100.00
V2	burst_write	kmac_burst_write	731.970s	9855.580us	2	2	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2039.530s	101860.688us	2	2	100.00
		kmac_test_vectors_sha3_256	1135.020s	54778.764us	2	2	100.00
		kmac_test_vectors_sha3_384	1113.720s	96525.144us	2	2	100.00
		kmac_test_vectors_sha3_512	804.410s	74270.327us	2	2	100.00
		kmac_test_vectors_shake_128	1369.720s	20159.025us	2	2	100.00
		kmac_test_vectors_shake_256	1458.540s	99372.984us	2	2	100.00
		kmac_test_vectors_kmac	2.720s	64.600us	2	2	100.00
		kmac_test_vectors_kmac_xof	2.440s	309.720us	2	2	100.00
V2	sideload	kmac_sideload	230.920s	15947.556us	2	2	100.00
V2	app	kmac_app	256.220s	61748.393us	2	2	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	132.580s	9383.541us	2	2	100.00
V2	entropy_refresh	kmac_entropy_refresh	252.070s	70116.086us	2	2	100.00
V2	error	kmac_error	156.500s	7771.387us	2	2	100.00
V2	key_error	kmac_key_error	8.050s	1166.893us	2	2	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.090s	172.573us	2	2	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.080s	1467.671us	2	2	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.630s	5960.093us	2	2	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	59.960s	110407.498us	2	2	100.00
V2	lc_escalation	kmac_lc_escalation	1.430s	33.735us	2	2	100.00
V2	stress_all	kmac_stress_all	1041.930s	254483.715us	2	2	100.00
V2	intr_test	kmac_intr_test	0.780s	17.086us	2	2	100.00
V2	alert_test	kmac_alert_test	0.880s	23.685us	2	2	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.060s	54.434us	2	2	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.060s	54.434us	2	2	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.950s	29.640us	2	2	100.00
		kmac_csr_rw	1.020s	36.190us	2	2	100.00
		kmac_csr_aliasing	3.300s	81.104us	2	2	100.00
		kmac_same_csr_outstanding	1.640s	37.519us	2	2	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.950s	29.640us	2	2	100.00
		kmac_csr_rw	1.020s	36.190us	2	2	100.00
		kmac_csr_aliasing	3.300s	81.104us	2	2	100.00
		kmac_same_csr_outstanding	1.640s	37.519us	2	2	100.00
V2		TOTAL			52	52	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.570s	98.100us	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.570s	98.100us	2	2	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.570s	98.100us	2	2	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.570s	98.100us	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.480s	2577.579us	2	2	100.00
V2S	tl_intg_err	kmac_sec_cm	48.600s	22716.911us	2	2	100.00
		kmac_tl_intg_err	4.460s	1488.632us	2	2	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.460s	1488.632us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.430s	33.735us	2	2	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.150s	3223.187us	2	2	100.00
V2S	sec_cm_key_sideload	kmac_sideload	230.920s	15947.556us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.570s	98.100us	2	2	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.600s	22716.911us	2	2	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.600s	22716.911us	2	2	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.600s	22716.911us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.150s	3223.187us	2	2	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.430s	33.735us	2	2	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.600s	22716.911us	2	2	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	106.340s	9878.006us	2	2	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.150s	3223.187us	2	2	100.00
V2S		TOTAL			10	10	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.480s	1878.042us	1	2	50.00
V3		TOTAL			1	2	50.00
		TOTAL			79	80	98.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.51	98.96	90.63	99.40	65.49	96.26	95.81	94.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.75060452567013197346241079678094003112197026066017128326277046667863178320493
      Line 241, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1878041696 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1878041696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---