OTBN Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	201.840us	1	1	100.00
V1	single_binary	otbn_single	7.000s	42.072us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	4.000s	30.017us	1	1	100.00
V1	csr_rw	otbn_csr_rw	4.000s	42.244us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	39.898us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	3.000s	140.813us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	35.821us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	4.000s	42.244us	1	1	100.00
		otbn_csr_aliasing	3.000s	140.813us	1	1	100.00
V1	mem_walk	otbn_mem_walk	39.000s	1825.735us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	372.053us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	18.000s	72.751us	1	1	100.00
V2	multi_error	otbn_multi_err	52.000s	155.467us	1	1	100.00
V2	back_to_back	otbn_multi	41.000s	2285.683us	1	1	100.00
V2	stress_all	otbn_stress_all	61.000s	209.882us	1	1	100.00
V2	lc_escalation	otbn_escalate	5.000s	55.557us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	6.000s	28.352us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	25.059us	1	1	100.00
V2	alert_test	otbn_alert_test	4.000s	29.747us	1	1	100.00
V2	intr_test	otbn_intr_test	4.000s	21.813us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	5.000s	129.662us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	5.000s	129.662us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	4.000s	30.017us	1	1	100.00
		otbn_csr_rw	4.000s	42.244us	1	1	100.00
		otbn_csr_aliasing	3.000s	140.813us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	26.831us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	4.000s	30.017us	1	1	100.00
		otbn_csr_rw	4.000s	42.244us	1	1	100.00
		otbn_csr_aliasing	3.000s	140.813us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	26.831us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	16.588us	1	1	100.00
		otbn_dmem_err	7.000s	16.600us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	6.000s	52.118us	1	1	100.00
		otbn_controller_ispr_rdata_err	5.000s	19.052us	1	1	100.00
		otbn_mac_bignum_acc_err	6.000s	55.027us	1	1	100.00
		otbn_urnd_err	7.000s	87.133us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	5.000s	19.504us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	5.000s	12.509us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	18.980us	1	1	100.00
V2S	tl_intg_err	otbn_tl_intg_err	12.000s	119.300us	1	1	100.00
		otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	382.785us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	201.840us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	7.000s	16.600us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	16.588us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	12.000s	119.300us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	5.000s	55.557us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	16.588us	1	1	100.00
		otbn_dmem_err	7.000s	16.600us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	28.352us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	19.504us	1	1	100.00
		otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	16.588us	1	1	100.00
		otbn_dmem_err	7.000s	16.600us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	28.352us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	19.504us	1	1	100.00
		otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	5.000s	55.557us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	16.588us	1	1	100.00
		otbn_dmem_err	7.000s	16.600us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	28.352us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	19.504us	1	1	100.00
		otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	6.000s	12.491us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	30.157us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	31.000s	351.391us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	31.000s	351.391us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	7.000s	146.873us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	64.298us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	27.625us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	27.625us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	4.000s	15.718us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	41.000s	2285.683us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	5.000s	36.467us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	42.072us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.000s	92.092us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	35.000s	799.632us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.66	99.46	93.43	99.57	91.06	91.76	94.87	86.89	93.59

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.86703052165699757617091793857506512594209277857869616769060396544542373040419
      Line 178, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 799632446 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 799632446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.2958805042176772504348915990389842035222515308777926340905780427452956002616
      Line 89, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 92092054 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 92092054 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 92092054 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 92092054 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 92092054 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed