PATTGEN Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: `38a9e0c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	26.977us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	13.268us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	26.197us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	99.588us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	22.938us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	40.037us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	26.197us	1	1	100.00
		pattgen_csr_aliasing	2.000s	22.938us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	22.000s	11047.667us	1	1	100.00
V2	cnt_rollover	cnt_rollover	20.000s	2688.250us	1	1	100.00
V2	error	pattgen_error	2.000s	128.925us	1	1	100.00
V2	stress_all	pattgen_stress_all	7072.000s	5685674.918us	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	95.462us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	13.965us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	149.629us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	149.629us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	13.268us	1	1	100.00
		pattgen_csr_rw	2.000s	26.197us	1	1	100.00
		pattgen_csr_aliasing	2.000s	22.938us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	35.371us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	13.268us	1	1	100.00
		pattgen_csr_rw	2.000s	26.197us	1	1	100.00
		pattgen_csr_aliasing	2.000s	22.938us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	35.371us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_sec_cm	1.000s	521.607us	1	1	100.00
		pattgen_tl_intg_err	2.000s	264.610us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	264.610us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	48.000s	9723.400us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	48.252us	1	1	100.00
		TOTAL			16	18	88.89

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	100.00	100.00	100.00	98.13	96.61	--	96.04	89.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.17864658125392646132237098920388009178977161850342749560239992563064287735972
Line 168, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2301540743 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2301541850 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2301541850 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 2301666850 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.37559286113029964646344945257936994311327574031434639305240207759422241121679
    Line 144, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 5685674917611 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10176
```