ROM_CTRL/64KB Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.940s	180.111us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.010s	1089.121us	2	2	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.430s	4980.403us	2	2	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.810s	393.164us	2	2	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.740s	289.756us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.400s	228.633us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.430s	4980.403us	2	2	100.00
		rom_ctrl_csr_aliasing	8.740s	289.756us	2	2	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.900s	300.149us	2	2	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.470s	393.525us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.130s	1097.773us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.880s	1295.059us	2	2	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.930s	393.971us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.320s	298.170us	2	2	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.960s	1074.876us	2	2	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.960s	1074.876us	2	2	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.010s	1089.121us	2	2	100.00
		rom_ctrl_csr_rw	7.430s	4980.403us	2	2	100.00
		rom_ctrl_csr_aliasing	8.740s	289.756us	2	2	100.00
		rom_ctrl_same_csr_outstanding	7.410s	300.145us	2	2	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.010s	1089.121us	2	2	100.00
		rom_ctrl_csr_rw	7.430s	4980.403us	2	2	100.00
		rom_ctrl_csr_aliasing	8.740s	289.756us	2	2	100.00
		rom_ctrl_same_csr_outstanding	7.410s	300.145us	2	2	100.00
V2		TOTAL			12	12	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.490s	2037.498us	2	2	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
		rom_ctrl_tl_intg_err	98.410s	845.915us	2	2	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.940s	180.111us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.940s	180.111us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.940s	180.111us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	98.410s	845.915us	2	2	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
		rom_ctrl_kmac_err_chk	12.930s	393.971us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	186.750s	5500.894us	2	2	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.490s	2037.498us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	459.260s	2680.638us	0	2	0.00
V2S		TOTAL			6	8	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	226.300s	2971.356us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			36	38	94.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.59	94.65	98.98	100.00	98.91	95.49	96.90

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.73032439930350153175548396928491558885955900439050112510758003269241909503375
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 1786101ps failed at 1786101ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1786101ps failed at 1786101ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.115167960650199767263899495671349034807186216418723776799440355889542357692890
      Line 289, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 60703437ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 60703437ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 60703437ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))