RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.620s 475.977us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.800s 330.754us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.830s 682.127us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.810s 16630.773us 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.150s 952.382us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 2.030s 3114.648us 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.020s 4913.802us 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 6.810s 12162.046us 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 12.100s 32072.918us 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.160s 931.169us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.520s 828.297us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 0.850s 175.711us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.870s 213.015us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.120s 235.884us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.840s 240.267us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.650s 81.450us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.330s 430.576us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.160s 931.169us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.880s 122.322us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.450s 481.171us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.850s 175.711us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 0.810s 228.694us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 1.760s 1469.635us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 1.840s 1457.936us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 22.230s 2559.211us 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 48.830s 17653.542us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 0.800s 105.023us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 48.830s 17653.542us 1 1 100.00
rv_dm_csr_rw 1.840s 1457.936us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 0.680s 31.370us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.630s 47.708us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 1.620s 475.977us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.020s 368.404us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.810s 116.199us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.760s 258.371us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.810s 323.713us 1 1 100.00
V2 sba rv_dm_sba_tl_access 111.070s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 564.530s 300000.000us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 69.830s 300000.000us 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 144.360s 300000.000us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.810s 114.413us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 1.250s 652.701us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 0.840s 181.897us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 0.730s 116.800us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm_rand_reset 0.730s 25.276us 0 1 0.00
rv_dm_tap_fsm 33.440s 18111.272us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 0.760s 409.037us 1 1 100.00
V2 stress_all rv_dm_stress_all 3.340s 1647.717us 1 1 100.00
V2 alert_test rv_dm_alert_test 0.750s 146.218us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 0.710s 50.883us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 0.710s 50.883us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 48.830s 17653.542us 1 1 100.00
rv_dm_csr_hw_reset 1.760s 1469.635us 1 1 100.00
rv_dm_csr_rw 1.840s 1457.936us 1 1 100.00
rv_dm_same_csr_outstanding 4.360s 595.806us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 48.830s 17653.542us 1 1 100.00
rv_dm_csr_hw_reset 1.760s 1469.635us 1 1 100.00
rv_dm_csr_rw 1.840s 1457.936us 1 1 100.00
rv_dm_same_csr_outstanding 4.360s 595.806us 1 1 100.00
V2 TOTAL 12 19 63.16
V2S tl_intg_err rv_dm_tl_intg_err 12.930s 2204.732us 1 1 100.00
rv_dm_sec_cm 1.500s 643.651us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 12.930s 2204.732us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 1.250s 652.701us 1 1 100.00
rv_dm_debug_disabled 0.820s 112.418us 0 1 0.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 1.250s 652.701us 1 1 100.00
rv_dm_debug_disabled 0.820s 112.418us 0 1 0.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 1.620s 475.977us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 0.820s 290.640us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.750s 63.729us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.750s 63.729us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 0.820s 290.640us 1 1 100.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0.740s 30.203us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 0.620s 17.825us 1 1 100.00
TOTAL 43 53 81.13

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
77.92 94.19 83.50 72.47 74.03 85.17 95.23 40.82

Failure Buckets