RV_TIMER Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.920s	805.890us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	41.044us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.590s	17.322us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.620s	284.573us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.630s	37.938us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.000s	27.419us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.590s	17.322us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	37.938us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	8.080s	8243.185us	0	1	0.00
V2	disabled	rv_timer_disabled	1.380s	3176.901us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	125.390s	205320.778us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	125.390s	205320.778us	1	1	100.00
V2	stress	rv_timer_stress_all	5.060s	8307.671us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.540s	33.932us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.630s	14.030us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.800s	110.610us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.800s	110.610us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	41.044us	1	1	100.00
		rv_timer_csr_rw	0.590s	17.322us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	37.938us	1	1	100.00
		rv_timer_same_csr_outstanding	0.710s	50.590us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	41.044us	1	1	100.00
		rv_timer_csr_rw	0.590s	17.322us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	37.938us	1	1	100.00
		rv_timer_same_csr_outstanding	0.710s	50.590us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.720s	128.545us	1	1	100.00
		rv_timer_tl_intg_err	1.340s	155.594us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.340s	155.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.790s	90.918us	0	1	0.00
V3	max_value	rv_timer_max	0.570s	44.386us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	9.230s	1635.799us	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.85	100.00	100.00	100.00	--	100.00	96.82	90.29

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.27290109396044247732208607010388936861885466472090205466418110124687120016347
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  90917882 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3fa0bf04) == 0x1
        UVM_INFO @  90917882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.32832626046304023723620961710893321389164280255759359386411047012031027155477
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 8243185490 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd577a304) == 0x1
        UVM_INFO @ 8243185490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.30804522022876337941662859437643107302801757530943300019322119813202402612219
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  44385570 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  44385570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---