SPI_DEVICE/2P Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	27.880s	34646.900us	2	2	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.140s	183.740us	2	2	100.00
V1	csr_rw	spi_device_csr_rw	1.150s	43.361us	2	2	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.190s	707.010us	2	2	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.670s	388.758us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.120s	98.666us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.150s	43.361us	2	2	100.00
		spi_device_csr_aliasing	5.670s	388.758us	2	2	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	24.946us	2	2	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.070s	128.069us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	csb_read	spi_device_csb_read	0.740s	29.439us	2	2	100.00
V2	mem_parity	spi_device_mem_parity	0.840s	29.457us	1	2	50.00
V2	mem_cfg	spi_device_ram_cfg	0.670s	3.585us	1	2	50.00
V2	tpm_read	spi_device_tpm_rw	5.170s	146.672us	2	2	100.00
V2	tpm_write	spi_device_tpm_rw	5.170s	146.672us	2	2	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.760s	2358.824us	2	2	100.00
		spi_device_tpm_sts_read	0.740s	10.961us	2	2	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	21.530s	27212.961us	2	2	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	11.010s	16067.799us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.800s	4132.735us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.800s	4132.735us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_info_slots	spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_read_status	spi_device_intercept	2.460s	302.249us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_read_jedec	spi_device_intercept	2.460s	302.249us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.460s	302.249us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_fast_read	spi_device_intercept	2.460s	302.249us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.460s	302.249us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	flash_cmd_upload	spi_device_upload	7.710s	3739.547us	2	2	100.00
V2	mailbox_command	spi_device_mailbox	66.300s	9961.959us	2	2	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	66.300s	9961.959us	2	2	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	66.300s	9961.959us	2	2	100.00
V2	cmd_read_buffer	spi_device_flash_mode	16.690s	1757.752us	2	2	100.00
		spi_device_read_buffer_direct	10.110s	7490.379us	2	2	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	66.300s	9961.959us	2	2	100.00
		spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	quad_spi	spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	dual_spi	spi_device_flash_all	89.480s	20662.811us	2	2	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.910s	148.789us	2	2	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.910s	148.789us	2	2	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	27.880s	34646.900us	2	2	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	178.030s	33903.557us	2	2	100.00
V2	stress_all	spi_device_stress_all	272.610s	66706.540us	2	2	100.00
V2	alert_test	spi_device_alert_test	0.700s	14.530us	2	2	100.00
V2	intr_test	spi_device_intr_test	0.720s	26.578us	2	2	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.140s	478.037us	2	2	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.140s	478.037us	2	2	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.140s	183.740us	2	2	100.00
		spi_device_csr_rw	1.150s	43.361us	2	2	100.00
		spi_device_csr_aliasing	5.670s	388.758us	2	2	100.00
		spi_device_same_csr_outstanding	2.950s	192.701us	2	2	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.140s	183.740us	2	2	100.00
		spi_device_csr_rw	1.150s	43.361us	2	2	100.00
		spi_device_csr_aliasing	5.670s	388.758us	2	2	100.00
		spi_device_same_csr_outstanding	2.950s	192.701us	2	2	100.00
V2		TOTAL			42	44	95.45
V2S	tl_intg_err	spi_device_sec_cm	0.880s	121.476us	2	2	100.00
		spi_device_tl_intg_err	9.400s	578.226us	2	2	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.400s	578.226us	2	2	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	14.710s	3372.841us	2	2	100.00
		TOTAL			64	66	96.97

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.60	99.07	95.60	87.74	87.23	98.28	94.27	72.02

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.48091582176990533641997855620804650263353436202383895955505511624092271213104
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2750957 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[3])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2750957 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2750957 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[899])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.18934273132105172770577880768467894040812067049034880961338162660476825196668
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    854645 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11da68 [100011101101001101000] vs 0x0 [0])
        UVM_ERROR @    893645 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe55bbe [111001010101101110111110] vs 0x0 [0])
        UVM_ERROR @    950645 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57ae56 [10101111010111001010110] vs 0x0 [0])
        UVM_ERROR @    982645 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa88d85 [101010001000110110000101] vs 0x0 [0])
        UVM_ERROR @   1035645 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xece629 [111011001110011000101001] vs 0x0 [0])