SPI_HOST Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	359.215us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	19.099us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	31.844us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	621.946us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	179.192us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	60.233us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	31.844us	1	1	100.00
		spi_host_csr_aliasing	2.000s	179.192us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	17.698us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	24.992us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	51.442us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	240.332us	1	1	100.00
		spi_host_error_cmd	2.000s	49.438us	1	1	100.00
		spi_host_event	32.000s	2332.236us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	296.220us	1	1	100.00
V2	speed	spi_host_speed	3.000s	296.220us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	296.220us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	63.921us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	194.295us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	296.220us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	296.220us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	359.215us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	359.215us	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	70.126us	1	1	100.00
V2	spien	spi_host_spien	70.000s	28365.937us	1	1	100.00
V2	stall	spi_host_status_stall	3.000s	70.086us	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	65.944us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	240.332us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	75.077us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	56.051us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	130.114us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	130.114us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	19.099us	1	1	100.00
		spi_host_csr_rw	1.000s	31.844us	1	1	100.00
		spi_host_csr_aliasing	2.000s	179.192us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	72.105us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	19.099us	1	1	100.00
		spi_host_csr_rw	1.000s	31.844us	1	1	100.00
		spi_host_csr_aliasing	2.000s	179.192us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	72.105us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_sec_cm	2.000s	797.162us	1	1	100.00
		spi_host_tl_intg_err	2.000s	100.921us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	100.921us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	150.000s	12748.191us	1	1	100.00
		TOTAL			25	26	96.15

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.00	96.26	92.15	98.47	88.50	88.02	100.00	93.12	88.75

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:
  • Test spi_host_status_stall has 1 failures.

    • 0.spi_host_status_stall.71478586906851880979838391038197010147801383873191578136214982504319206331663
      Line 811, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 70085877 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @  70085877 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time= 70086000 ps
        UVM_INFO @  70085877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---