SRAM_CTRL/RET Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	47.020s	514.836us	2	2	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	40.171us	2	2	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	48.020us	2	2	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.610s	92.058us	2	2	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	12.400us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.390s	1308.457us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	48.020us	2	2	100.00
		sram_ctrl_csr_aliasing	0.820s	12.400us	2	2	100.00
V1	mem_walk	sram_ctrl_mem_walk	110.050s	5479.851us	2	2	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	60.210s	3040.711us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	652.620s	42039.205us	2	2	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	284.650s	5354.914us	2	2	100.00
V2	bijection	sram_ctrl_bijection	459.880s	9930.743us	2	2	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	489.750s	12383.786us	2	2	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	40.050s	13431.621us	2	2	100.00
V2	executable	sram_ctrl_executable	597.180s	41524.246us	2	2	100.00
V2	partial_access	sram_ctrl_partial_access	53.110s	1579.805us	2	2	100.00
		sram_ctrl_partial_access_b2b	344.860s	34379.248us	2	2	100.00
V2	max_throughput	sram_ctrl_max_throughput	52.010s	201.781us	2	2	100.00
		sram_ctrl_throughput_w_partial_write	18.290s	143.786us	2	2	100.00
		sram_ctrl_throughput_w_readback	40.890s	508.617us	2	2	100.00
V2	regwen	sram_ctrl_regwen	360.970s	2779.409us	2	2	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.950s	1334.432us	2	2	100.00
V2	stress_all	sram_ctrl_stress_all	3985.110s	2201542.721us	2	2	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	36.174us	2	2	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.470s	479.257us	2	2	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.470s	479.257us	2	2	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	40.171us	2	2	100.00
		sram_ctrl_csr_rw	0.850s	48.020us	2	2	100.00
		sram_ctrl_csr_aliasing	0.820s	12.400us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.910s	64.284us	2	2	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	40.171us	2	2	100.00
		sram_ctrl_csr_rw	0.850s	48.020us	2	2	100.00
		sram_ctrl_csr_aliasing	0.820s	12.400us	2	2	100.00
		sram_ctrl_same_csr_outstanding	0.910s	64.284us	2	2	100.00
V2		TOTAL			34	34	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.880s	7304.077us	2	2	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
		sram_ctrl_tl_intg_err	2.270s	432.907us	2	2	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.270s	432.907us	2	2	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	360.970s	2779.409us	2	2	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	360.970s	2779.409us	2	2	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	48.020us	2	2	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	597.180s	41524.246us	2	2	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	597.180s	41524.246us	2	2	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	597.180s	41524.246us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	40.050s	13431.621us	2	2	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.410s	702.646us	2	2	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.880s	7304.077us	2	2	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.040s	698.645us	1	2	50.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	47.020s	514.836us	2	2	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	47.020s	514.836us	2	2	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	597.180s	41524.246us	2	2	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	40.050s	13431.621us	2	2	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	47.020s	514.836us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.730s	1.359us	0	2	0.00
V2S		TOTAL			7	10	70.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	132.490s	2968.000us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			59	62	95.16

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.32	97.68	91.19	90.47	80.95	94.70	95.51	95.73

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.9035693396531141708667584454204343841313763100574125649492942072200577221481
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1359222 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1359222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.18736998725007518350535318912895754741904142371821232400853099558357531449872
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  36147420 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x75) != exp (0x23)
        UVM_INFO @  36147420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.63048652542617595145939457297128940044921536484764305829322106594035375788303
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3503679 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3503679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---