SYSRST_CTRL Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.800s	2126.071us	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.070s	2485.126us	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.300s	2211.791us	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.580s	2313.978us	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	2.170s	4099.454us	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.310s	2119.517us	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	22.160s	39093.619us	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.040s	2821.265us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.610s	2165.440us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.310s	2119.517us	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.040s	2821.265us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	81.080s	42401.933us	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	319.210s	168457.957us	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.750s	3334.124us	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	4.300s	5495.536us	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	1.530s	2542.648us	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.710s	2172.532us	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.960s	2549.304us	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.840s	2629.729us	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	59.430s	496680.650us	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	21.020s	37477.683us	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	343.260s	177300.108us	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.330s	2010.933us	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.720s	2016.994us	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.680s	2160.376us	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.680s	2160.376us	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	2.170s	4099.454us	1	1	100.00
		sysrst_ctrl_csr_rw	2.310s	2119.517us	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.040s	2821.265us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	29.960s	9918.584us	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	2.170s	4099.454us	1	1	100.00
		sysrst_ctrl_csr_rw	2.310s	2119.517us	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.040s	2821.265us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	29.960s	9918.584us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	21.000s	42173.905us	1	1	100.00
		sysrst_ctrl_tl_intg_err	80.460s	42478.011us	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	80.460s	42478.011us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.300s	32380.899us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.78	96.30	93.93	100.00	69.23	96.81	90.52	74.66