UART Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: 38a9e0c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.590s	5561.379us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	14.772us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.650s	14.888us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.220s	538.029us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.690s	60.713us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.850s	80.682us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	14.888us	1	1	100.00
		uart_csr_aliasing	0.690s	60.713us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	24.670s	23152.979us	1	1	100.00
V2	parity	uart_smoke	6.590s	5561.379us	1	1	100.00
		uart_tx_rx	24.670s	23152.979us	1	1	100.00
V2	parity_error	uart_intr	10.650s	20398.372us	1	1	100.00
		uart_rx_parity_err	8.650s	28115.347us	1	1	100.00
V2	watermark	uart_tx_rx	24.670s	23152.979us	1	1	100.00
		uart_intr	10.650s	20398.372us	1	1	100.00
V2	fifo_full	uart_fifo_full	14.020s	11807.928us	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	45.480s	33163.523us	1	1	100.00
V2	fifo_reset	uart_fifo_reset	91.310s	150035.010us	1	1	100.00
V2	rx_frame_err	uart_intr	10.650s	20398.372us	1	1	100.00
V2	rx_break_err	uart_intr	10.650s	20398.372us	1	1	100.00
V2	rx_timeout	uart_intr	10.650s	20398.372us	1	1	100.00
V2	perf	uart_perf	300.130s	16807.327us	1	1	100.00
V2	sys_loopback	uart_loopback	5.690s	5932.996us	1	1	100.00
V2	line_loopback	uart_loopback	5.690s	5932.996us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	75.510s	59517.067us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.460s	2868.441us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	15.520s	6865.898us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.360s	6842.707us	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	368.180s	74183.973us	1	1	100.00
V2	stress_all	uart_stress_all	194.430s	422676.334us	1	1	100.00
V2	alert_test	uart_alert_test	0.530s	11.896us	1	1	100.00
V2	intr_test	uart_intr_test	0.580s	46.547us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.060s	60.163us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.060s	60.163us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	14.772us	1	1	100.00
		uart_csr_rw	0.650s	14.888us	1	1	100.00
		uart_csr_aliasing	0.690s	60.713us	1	1	100.00
		uart_same_csr_outstanding	0.720s	30.579us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	14.772us	1	1	100.00
		uart_csr_rw	0.650s	14.888us	1	1	100.00
		uart_csr_aliasing	0.690s	60.713us	1	1	100.00
		uart_same_csr_outstanding	0.720s	30.579us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.790s	250.665us	1	1	100.00
		uart_tl_intg_err	1.080s	109.359us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.080s	109.359us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.350s	5321.514us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.81	99.17	95.22	91.32	--	97.44	97.12	58.62

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.71224344298892606371832243932165156046403778475750458442735947149828032602824
      Line 87, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 58317274674 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 58317274674 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 59465625111 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 17/19
        UVM_ERROR @ 59468851828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 59476325853 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0