CHIP Simulation Results

Thursday November 13 2025 19:23:53 UTC

GitHub Revision: `38a9e0c`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	101.460s	2529.833us	1	1	100.00
		chip_sw_example_rom	72.150s	2827.723us	1	1	100.00
		chip_sw_example_manufacturer	171.410s	3312.279us	1	1	100.00
		chip_sw_example_concurrency	153.940s	2329.452us	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	229.910s	6346.005us	1	1	100.00
V1	csr_rw	chip_csr_rw	362.850s	5900.983us	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2002.990s	31042.848us	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	4724.430s	37150.665us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	682.340s	11579.584us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	4724.430s	37150.665us	1	1	100.00
		chip_csr_rw	362.850s	5900.983us	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.860s	41.276us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	349.340s	4650.518us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	349.340s	4650.518us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	349.340s	4650.518us	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	392.060s	4266.601us	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	392.060s	4266.601us	1	1	100.00
		chip_sw_uart_tx_rx_idx1	372.780s	4132.239us	1	1	100.00
		chip_sw_uart_tx_rx_idx2	343.420s	3512.737us	1	1	100.00
		chip_sw_uart_tx_rx_idx3	407.970s	4092.146us	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	307.480s	3452.254us	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1068.290s	8471.254us	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	237.320s	3673.068us	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	259.520s	6139.265us	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	259.520s	6139.265us	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	152.690s	3209.651us	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	112.980s	2219.725us	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	173.460s	3382.892us	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	172.680s	4430.967us	1	1	100.00
		chip_tap_straps_testunlock0	243.580s	4707.245us	1	1	100.00
		chip_tap_straps_rma	325.500s	5746.137us	1	1	100.00
		chip_tap_straps_prod	735.560s	11511.563us	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	146.920s	2899.469us	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	818.130s	8184.540us	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	399.840s	6073.315us	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	399.840s	6073.315us	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	551.290s	7456.109us	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	2231.270s	23207.597us	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	374.970s	4391.141us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	538.390s	5997.576us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3437.880s	18635.086us	1	1	100.00
		chip_sw_aes_enc_jitter_en	194.480s	2573.186us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	497.290s	5024.029us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	163.990s	3116.601us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1212.760s	9995.365us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	186.930s	2931.637us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	383.100s	5360.551us	1	1	100.00
		chip_sw_clkmgr_jitter	108.330s	3039.924us	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	188.340s	2824.116us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	186.980s	4021.193us	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	266.450s	4932.540us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	160.040s	3104.096us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	266.450s	4932.540us	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	142.030s	2529.757us	1	1	100.00
		chip_sw_aes_smoketest	189.500s	3514.573us	1	1	100.00
		chip_sw_aon_timer_smoketest	168.720s	2924.758us	1	1	100.00
		chip_sw_clkmgr_smoketest	135.820s	3204.050us	1	1	100.00
		chip_sw_csrng_smoketest	139.730s	3041.737us	1	1	100.00
		chip_sw_entropy_src_smoketest	712.910s	6129.414us	1	1	100.00
		chip_sw_gpio_smoketest	165.100s	3094.489us	1	1	100.00
		chip_sw_hmac_smoketest	209.220s	3266.467us	1	1	100.00
		chip_sw_kmac_smoketest	218.470s	2953.881us	1	1	100.00
		chip_sw_otbn_smoketest	1236.420s	11120.090us	1	1	100.00
		chip_sw_pwrmgr_smoketest	249.130s	5886.356us	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	229.420s	5190.475us	1	1	100.00
		chip_sw_rv_plic_smoketest	183.920s	3451.703us	1	1	100.00
		chip_sw_rv_timer_smoketest	132.520s	3211.949us	1	1	100.00
		chip_sw_rstmgr_smoketest	139.690s	2826.702us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	112.650s	2678.774us	1	1	100.00
		chip_sw_uart_smoketest	131.860s	2785.172us	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	123.410s	2908.481us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	328.060s	5043.324us	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	8127.010s	61777.996us	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2552.450s	15398.559us	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	156.850s	4919.597us	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	171.690s	2916.635us	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	184.900s	3093.222us	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	7297.600s	54989.282us	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	7144.250s	56820.186us	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	49.120s	2301.996us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	49.120s	2301.996us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	4724.430s	37150.665us	1	1	100.00
		chip_same_csr_outstanding	1380.700s	16240.049us	1	1	100.00
		chip_csr_hw_reset	229.910s	6346.005us	1	1	100.00
		chip_csr_rw	362.850s	5900.983us	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	4724.430s	37150.665us	1	1	100.00
		chip_same_csr_outstanding	1380.700s	16240.049us	1	1	100.00
		chip_csr_hw_reset	229.910s	6346.005us	1	1	100.00
		chip_csr_rw	362.850s	5900.983us	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	18.480s	718.723us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.410s	41.898us	1	1	100.00
		xbar_smoke_large_delays	40.360s	6547.949us	1	1	100.00
		xbar_smoke_slow_rsp	47.830s	5566.007us	1	1	100.00
		xbar_random_zero_delays	5.400s	42.743us	1	1	100.00
		xbar_random_large_delays	145.160s	24633.361us	1	1	100.00
		xbar_random_slow_rsp	163.930s	17884.237us	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	17.060s	523.096us	1	1	100.00
		xbar_error_and_unmapped_addr	11.100s	132.460us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.730s	226.891us	1	1	100.00
		xbar_error_and_unmapped_addr	11.100s	132.460us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	58.370s	2178.697us	1	1	100.00
		xbar_access_same_device_slow_rsp	187.670s	21262.452us	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	39.660s	2133.871us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	344.680s	15061.769us	1	1	100.00
		xbar_stress_all_with_error	219.430s	10239.505us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	173.350s	1324.771us	1	1	100.00
		xbar_stress_all_with_reset_error	65.020s	478.339us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	2552.450s	15398.559us	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	2362.460s	30618.480us	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2591.690s	15201.540us	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2005.360s	13308.197us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2656.870s	16157.484us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2589.880s	16043.278us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2651.650s	15721.637us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2548.900s	16670.036us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.830s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.890s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.620s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.900s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.520s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.920s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.500s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.720s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.150s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.460s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.920s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	24.470s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	22.570s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.510s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.860s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.910s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.020s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.550s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.760s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.890s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.890s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.160s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.180s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.740s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.030s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	2006.330s	11365.389us	1	1	100.00
		rom_e2e_asm_init_dev	2625.240s	15674.528us	1	1	100.00
		rom_e2e_asm_init_prod	2607.650s	17021.189us	1	1	100.00
		rom_e2e_asm_init_prod_end	2532.310s	16944.366us	1	1	100.00
		rom_e2e_asm_init_rma	2513.870s	15312.529us	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2377.430s	14889.597us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2418.340s	14517.120us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2374.000s	15229.201us	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2447.450s	15882.315us	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3072.220s	34539.978us	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3072.220s	34539.978us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	128.520s	2987.666us	1	1	100.00
		chip_sw_aes_enc_jitter_en	194.480s	2573.186us	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	109.330s	2936.429us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	144.240s	2651.642us	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	982.880s	8187.764us	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	151.020s	3347.720us	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	294.560s	4741.799us	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	606.920s	5979.581us	1	1	100.00
		chip_plic_all_irqs_10	299.700s	4208.909us	1	1	100.00
		chip_plic_all_irqs_20	379.410s	4121.337us	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	194.670s	3019.972us	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	1200.770s	15494.200us	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	260.340s	4000.259us	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	147.560s	2786.841us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	479.550s	5196.745us	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	773.790s	6047.053us	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	845.210s	7818.543us	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8797.560s	254880.844us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	226.860s	3772.567us	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	249.130s	5886.356us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	226.860s	3772.567us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	335.790s	7364.995us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	335.790s	7364.995us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	297.620s	7102.330us	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	389.480s	5963.154us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	548.420s	6110.516us	1	1	100.00
		chip_sw_aes_idle	144.240s	2651.642us	1	1	100.00
		chip_sw_hmac_enc_idle	179.480s	3465.238us	1	1	100.00
		chip_sw_kmac_idle	103.820s	2561.159us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	290.550s	4400.226us	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	197.230s	4086.450us	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	277.200s	3543.065us	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	325.590s	3954.928us	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	593.030s	8761.849us	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	362.550s	4452.580us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	343.910s	4190.197us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	426.900s	4410.523us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.200s	4416.470us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	385.630s	4139.940us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	377.440s	4064.099us	1	1	100.00
		chip_sw_ast_clk_outputs	551.290s	7456.109us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	550.080s	10579.406us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	426.900s	4410.523us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.200s	4416.470us	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	374.970s	4391.141us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	538.390s	5997.576us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3437.880s	18635.086us	1	1	100.00
		chip_sw_aes_enc_jitter_en	194.480s	2573.186us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	497.290s	5024.029us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	163.990s	3116.601us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1212.760s	9995.365us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	186.930s	2931.637us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	383.100s	5360.551us	1	1	100.00
		chip_sw_clkmgr_jitter	108.330s	3039.924us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	101.270s	3038.652us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	378.670s	5008.529us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	626.660s	7299.805us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3221.570s	24893.242us	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	165.510s	3412.112us	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	179.670s	2856.012us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	859.590s	9115.142us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	150.940s	2862.818us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	317.070s	4875.072us	1	1	100.00
		chip_sw_flash_init_reduced_freq	1125.320s	18246.233us	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3600.090s	35686.115us	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	551.290s	7456.109us	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	323.690s	3814.516us	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	284.840s	3369.216us	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	479.550s	5196.745us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	909.000s	6910.363us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	158.520s	2781.366us	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	390.080s	5538.342us	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	135.940s	2799.985us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1386.940s	8977.531us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	119.680s	2563.856us	1	1	100.00
		chip_sw_edn_entropy_reqs	783.590s	6671.544us	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	119.680s	2563.856us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	909.000s	6910.363us	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	146.550s	2769.857us	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1572.990s	24693.167us	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	548.300s	5753.323us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	538.390s	5997.576us	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	420.420s	4461.733us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	374.970s	4391.141us	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	3804.410s	44119.057us	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1572.990s	24693.167us	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	190.220s	3575.522us	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	3804.410s	44119.057us	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	365.100s	14493.607us	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	530.930s	4930.416us	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	336.030s	4793.736us	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	336.030s	4793.736us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	144.440s	2475.594us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	163.990s	3116.601us	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	179.480s	3465.238us	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	831.770s	6412.072us	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	343.000s	3520.998us	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	470.230s	5263.006us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	378.160s	5005.003us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	416.280s	5403.461us	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	249.400s	3963.773us	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1212.760s	9995.365us	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	690.630s	7482.435us	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	982.880s	8187.764us	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2956.880s	15822.266us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	173.380s	3395.723us	1	1	100.00
		chip_sw_kmac_mode_kmac	187.170s	2811.228us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	186.930s	2931.637us	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	143.420s	2889.270us	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	1249.130s	9531.982us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	103.820s	2561.159us	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	294.560s	4741.799us	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	172.680s	4430.967us	1	1	100.00
		chip_tap_straps_rma	325.500s	5746.137us	1	1	100.00
		chip_tap_straps_prod	735.560s	11511.563us	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	114.650s	2279.306us	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	1669.470s	12894.252us	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	365.100s	14493.607us	1	1	100.00
		chip_rv_dm_lc_disabled	131.540s	6486.013us	0	1	0.00
		chip_sw_flash_ctrl_lc_rw_en	223.220s	4294.168us	1	1	100.00
		chip_sw_flash_rma_unlocked	3804.410s	44119.057us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	205.790s	2765.832us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	651.130s	6756.801us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	586.880s	6446.701us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	497.230s	7407.875us	0	1	0.00
		chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
		chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	342.320s	9248.714us	1	1	100.00
		chip_sw_sram_ctrl_execution_main	438.940s	7586.948us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	550.080s	10579.406us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	362.550s	4452.580us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	343.910s	4190.197us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	426.900s	4410.523us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.200s	4416.470us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	385.630s	4139.940us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	377.440s	4064.099us	1	1	100.00
		chip_tap_straps_dev	172.680s	4430.967us	1	1	100.00
		chip_tap_straps_rma	325.500s	5746.137us	1	1	100.00
		chip_tap_straps_prod	735.560s	11511.563us	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	125.040s	3390.993us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	79.280s	3347.849us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	97.540s	2724.037us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1931.850s	26701.344us	0	1	0.00
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	131.540s	6486.013us	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	1416.150s	23448.689us	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	4160.400s	46791.529us	1	1	100.00
		chip_sw_lc_walkthrough_prod	3859.360s	51569.670us	1	1	100.00
		chip_sw_lc_walkthrough_prodend	557.910s	8494.428us	1	1	100.00
		chip_sw_lc_walkthrough_rma	3705.330s	44998.978us	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1416.150s	23448.689us	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	53.250s	2423.805us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	61.690s	2598.319us	1	1	100.00
		rom_volatile_raw_unlock	61.160s	2751.808us	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3281.040s	16735.296us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3437.880s	18635.086us	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	548.420s	6110.516us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	548.420s	6110.516us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	548.420s	6110.516us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	263.120s	2820.583us	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1572.990s	24693.167us	1	1	100.00
		chip_sw_otbn_mem_scramble	263.120s	2820.583us	1	1	100.00
		chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	266.040s	3580.131us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	133.640s	1997.731us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1572.990s	24693.167us	1	1	100.00
		chip_sw_otbn_mem_scramble	263.120s	2820.583us	1	1	100.00
		chip_sw_keymgr_key_derivation	1607.020s	11326.243us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	266.040s	3580.131us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	133.640s	1997.731us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	322.310s	4765.281us	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	114.650s	2279.306us	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	365.100s	14493.607us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	205.790s	2765.832us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	651.130s	6756.801us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	586.880s	6446.701us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	497.230s	7407.875us	0	1	0.00
		chip_sw_lc_ctrl_transition	339.850s	7022.514us	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	365.100s	14493.607us	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1047.540s	8652.242us	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	262.150s	7427.565us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	1044.800s	26278.711us	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	205.710s	7193.906us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	359.660s	8041.780us	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	392.910s	5687.402us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1334.850s	26357.603us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	187.960s	5522.547us	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	335.790s	7364.995us	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	665.750s	9402.345us	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	286.140s	3812.837us	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	262.150s	7427.565us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	181.350s	3897.484us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1562.740s	29392.213us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	309.280s	7219.116us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	307.220s	5193.998us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1452.570s	19377.633us	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	499.020s	6658.985us	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	943.770s	12044.481us	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1488.580s	26902.548us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	138.000s	2566.192us	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	342.320s	9248.714us	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	342.320s	9248.714us	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	943.770s	12044.481us	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1452.570s	19377.633us	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	286.140s	3812.837us	1	1	100.00
		chip_sw_pwrmgr_smoketest	249.130s	5886.356us	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	246.260s	4901.068us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	222.260s	3806.116us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	293.620s	4554.881us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	1200.770s	15494.200us	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	152.160s	2621.895us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	773.790s	6047.053us	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	445.410s	4145.128us	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	449.010s	4434.428us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	153.180s	2816.695us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	133.640s	1997.731us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	222.260s	3806.116us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	222.260s	3806.116us	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	1427.030s	18701.487us	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	919.630s	13450.390us	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	246.260s	4901.068us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	330.770s	5002.566us	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	336.150s	5731.765us	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	325.500s	5746.137us	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	131.540s	6486.013us	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	606.920s	5979.581us	1	1	100.00
		chip_plic_all_irqs_10	299.700s	4208.909us	1	1	100.00
		chip_plic_all_irqs_20	379.410s	4121.337us	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	151.810s	3346.913us	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	126.670s	2453.246us	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2552.450s	15398.559us	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	413.550s	6765.273us	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	181.490s	3354.610us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	181.600s	2810.218us	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	178.340s	2864.437us	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	266.040s	3580.131us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	383.100s	5360.551us	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	374.810s	6454.663us	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	435.900s	8865.040us	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	438.940s	7586.948us	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
		chip_sw_data_integrity_escalation	399.840s	6073.315us	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	499.020s	6658.985us	1	1	100.00
		chip_sw_sysrst_ctrl_reset	1221.140s	22611.758us	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	141.720s	3144.160us	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	175.150s	3799.232us	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	308.710s	4737.196us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	1221.140s	22611.758us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	1221.140s	22611.758us	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2431.930s	20083.604us	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2431.930s	20083.604us	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	232.290s	5505.042us	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3072.220s	34539.978us	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	136.820s	2915.107us	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	189.740s	3255.035us	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	296.320s	3286.475us	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	321.850s	3796.962us	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	1068.530s	8307.091us	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	5088.140s	32040.385us	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1793.630s	11717.427us	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	139.670s	2807.195us	1	1	100.00
V2		TOTAL			234	275	85.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	193.900s	2381.127us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	75.860s	2336.647us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	9338.220s	71860.775us	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1089.720s	6224.666us	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1178.460s	10680.254us	1	1	100.00
		rom_e2e_jtag_debug_dev	1136.150s	11246.569us	1	1	100.00
		rom_e2e_jtag_debug_rma	1150.830s	12153.746us	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	203.890s	5342.317us	1	1	100.00
		rom_e2e_jtag_inject_dev	153.220s	4362.638us	1	1	100.00
		rom_e2e_jtag_inject_rma	244.310s	3849.459us	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.593s	0.000us	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	507.770s	4809.685us	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	274.920s	2827.998us	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1164.430s	7124.422us	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	709.430s	5751.364us	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	218.540s	2694.154us	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	592.100s	4522.372us	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	60.540s	2143.451us	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	167.880s	3034.853us	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	195.660s	4544.419us	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	209.420s	4423.470us	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	943.770s	12044.481us	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1178.460s	10680.254us	1	1	100.00
		rom_e2e_jtag_debug_dev	1136.150s	11246.569us	1	1	100.00
		rom_e2e_jtag_debug_rma	1150.830s	12153.746us	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	322.160s	4884.523us	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	374.620s	4264.649us	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	5486.040s	38365.277us	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	5486.040s	38365.277us	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	174.580s	4028.138us	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	392.060s	4266.601us	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	3130.500s	18138.835us	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	171.700s	3146.890us	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	453.010s	4981.298us	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	1814.590s	32982.021us	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	148.120s	3349.204us	1	1	100.00
		chip_sw_otp_ctrl_descrambling	198.050s	3312.223us	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	242.810s	4128.190us	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.879s	0.000us	0	1	0.00
		chip_sw_flash_ctrl_write_clear	181.240s	3091.847us	1	1	100.00
		TOTAL			280	326	85.89

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.24	94.41	89.91	91.55	57.14	93.82	96.44	45.42

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.46282946775179942505827326304842686097531675148403652466272629364760450417895
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.115003815642875139958083900022117286611838175999565495150256043252862673600063
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.43571652762179048675540050757141704540853587606305360370309476764937805640173
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.21397513749451030751948260375358555872661360487622713069570976295367621915094
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.29417669833959721323009309901325898376564919653997906094940609920077347591665
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.50548983157423790210816488212893085926748612860085951739484481796575318170857
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.27219401011819925900878041300258309227956098495376970931513161707025043910598
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.43057277915424823267639315294247399446366963690073354321385833393639465695382
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.104648497389241952652695523973043399121735671525550446531256308362918495149245
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.28690258897928403504257949187809787061035039356735777152061398585360771137491
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.12065682960189418616897809711844597622820464260898037402940594419340366578208
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5522.546500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5522.546500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.72286526901720552421260144003892482808031592062028291489785560474564015209343
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 8041.780500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 8041.780500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.94795401507909044287011298986344162456647876260934203085905952604550390662000
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7364.995000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7364.995000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.52735185908336193142936563294015610093176904093025222188259892268468006879389
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.43256658080741972573534329653145325211280291188387541327281090753132006835066
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.36021398708899092676642646703488896557327192242778563153774459654748560731814
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.43342367745479373626125785368451963009419915512195138568253398494807980827999
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3034.852742 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3034.852742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.89041079407648449498213283107876344671360563248401709664360970762743333759395
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2781.365944 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2781.365944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.113492453292571230931894178770318130128018365046791172247971056105106912069347
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.113099708531114804788298324497265048355692402597179397845691506801572584108856
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.166s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.75717700765796727841865004999768495748347496066200626739018051414572885211463
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.12840492741441009737146844499926012080057310047125826620683081093758562031263
    Line 459, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.112070949114542273337585447392134041014554002007172457878706442646304511236993
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.98711407624727589723358938376416811922492204608882311825325314028775759350526
    Line 443, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31901) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.64666103722587899084806972290162924373451656213612753321265779497580018415892
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2301.996155 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31901) { a_addr: 'h107d0  a_data: 'hf0a2e512  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1a526  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2301.996155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.73471541109041145906305083156083629114619389785585890077173541639820766704021
    Line 228, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 6486.013062 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10784 read out mismatch
  UVM_INFO @ 6486.013062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.101465879660889849062380637535673151941053721483556983420766268456898990997236
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3354.610060 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3354.610060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.61861629486900182561952739811873662002831121672914629514171457278013129616664
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7407.874990 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7407.874990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.48214204854730678909284894780666701104258546038253302470529518462036700535434
    Line 445, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 32982.020760 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 32982.020760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:827) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.10498237413795139640136589316949543006638879272797515181785872701649897423276
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 26701.343848 us: (chip_sw_base_vseq.sv:827) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 26701.343848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82997) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.94865126051211231698619766065885995989957493863985050313410307953585480431350
Line 426, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3806.115621 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82997) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3806.115621 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.39200864864651270661441286957701527616054199066000070066122328568521263711250
    Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34539.977643 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34539.977643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.91255728474331938539277814724688583935729254731238596936351242649151322294099
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3347.719813 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3347.719813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.105938639842306844202534840123180487715102098459752507513249694773812981029954
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2786.841210 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2786.841210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.89610194249935506427938139473145733289136153333596990338742971215915901008079
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.37924161894320927665610292102595585345364431959775097004483758400302522704898
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 4128.189634 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 4128.189634 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.36108189206303824894148375286877695526276732115406590939280457947676279349201
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2916.635000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2916.635000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.97582670015204958048881902372738640319318998218356058677145648027229354346725
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3093.222000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3093.222000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.48437644158622170573504935803068285022291935630245287847171722542399079332411
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.33325481735291324764589578132984854074155424891886444439885055910265988445582
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```