ADC_CTRL Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.840s	5828.191us	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.970s	895.695us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.390s	414.043us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	4.220s	1094.754us	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.160s	740.519us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.040s	605.091us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.390s	414.043us	1	1	100.00
		adc_ctrl_csr_aliasing	3.160s	740.519us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	60.990s	494152.866us	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	308.840s	332352.777us	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	544.430s	335012.197us	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	587.470s	325691.782us	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	289.630s	359594.494us	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	292.020s	601995.233us	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	325.790s	177285.321us	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	60.010s	195497.170us	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.560s	3426.760us	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	32.490s	35304.517us	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	91.160s	93675.214us	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	397.830s	255069.106us	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.500s	422.422us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.510s	336.074us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.610s	382.829us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.610s	382.829us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.970s	895.695us	1	1	100.00
		adc_ctrl_csr_rw	1.390s	414.043us	1	1	100.00
		adc_ctrl_csr_aliasing	3.160s	740.519us	1	1	100.00
		adc_ctrl_same_csr_outstanding	1.540s	2861.669us	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.970s	895.695us	1	1	100.00
		adc_ctrl_csr_rw	1.390s	414.043us	1	1	100.00
		adc_ctrl_csr_aliasing	3.160s	740.519us	1	1	100.00
		adc_ctrl_same_csr_outstanding	1.540s	2861.669us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_tl_intg_err	4.940s	8497.581us	1	1	100.00
		adc_ctrl_sec_cm	16.980s	8130.159us	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.940s	8497.581us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.470s	14439.610us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.99	99.05	94.83	100.00	91.89	98.64	95.95	42.57