| V1 |
smoke |
aon_timer_smoke |
1.490s |
644.274us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.770s |
812.420us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
1.080s |
501.256us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
9.850s |
5801.412us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.260s |
602.611us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.700s |
478.680us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
1.080s |
501.256us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.260s |
602.611us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.860s |
418.659us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
0.810s |
270.014us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
0.950s |
913.433us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
0.990s |
661.231us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
2.120s |
1973.394us |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.850s |
281.301us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.890s |
394.694us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
2.050s |
451.830us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
2.050s |
451.830us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.770s |
812.420us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.080s |
501.256us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.260s |
602.611us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.010s |
3023.134us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.770s |
812.420us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.080s |
501.256us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.260s |
602.611us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.010s |
3023.134us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
5.000s |
4029.013us |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
11.460s |
8350.454us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
11.460s |
8350.454us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.960s |
681.718us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.380s |
672.180us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
1.310s |
3672.020us |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.800s |
563.601us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
3.210s |
4141.686us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
18.740s |
13304.364us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |