CSRNG Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.000s	36.730us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	18.682us	1	1	100.00
V1	csr_rw	csrng_csr_rw	3.000s	23.841us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	17.000s	454.253us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	174.191us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.000s	27.299us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	23.841us	1	1	100.00
		csrng_csr_aliasing	4.000s	174.191us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	4.000s	143.911us	1	1	100.00
V2	alerts	csrng_alert	5.000s	134.308us	1	1	100.00
V2	err	csrng_err	2.000s	33.324us	1	1	100.00
V2	cmds	csrng_cmds	128.000s	9567.658us	1	1	100.00
V2	life cycle	csrng_cmds	128.000s	9567.658us	1	1	100.00
V2	stress_all	csrng_stress_all	9.000s	163.182us	1	1	100.00
V2	intr_test	csrng_intr_test	2.000s	14.799us	1	1	100.00
V2	alert_test	csrng_alert_test	2.000s	54.524us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	4.000s	90.336us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	4.000s	90.336us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	18.682us	1	1	100.00
		csrng_csr_rw	3.000s	23.841us	1	1	100.00
		csrng_csr_aliasing	4.000s	174.191us	1	1	100.00
		csrng_same_csr_outstanding	4.000s	137.054us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	18.682us	1	1	100.00
		csrng_csr_rw	3.000s	23.841us	1	1	100.00
		csrng_csr_aliasing	4.000s	174.191us	1	1	100.00
		csrng_same_csr_outstanding	4.000s	137.054us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_tl_intg_err	3.000s	75.778us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_csr_rw	3.000s	23.841us	1	1	100.00
		csrng_regwen	2.000s	73.498us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	5.000s	134.308us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	9.000s	163.182us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	5.000s	134.308us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	9.000s	163.182us	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	5.000s	134.308us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	3.000s	75.778us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
		csrng_sec_cm	4.000s	239.430us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	4.000s	143.911us	1	1	100.00
		csrng_err	2.000s	33.324us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	149.000s	10284.344us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			19	19	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
93.98	96.56	91.56	97.49	94.65	91.65	66.67	92.18	67.86