HMAC Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	10.020s	1826.028us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.880s	16.329us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.760s	92.330us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.490s	4697.750us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.170s	2072.428us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.260s	39.654us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	92.330us	1	1	100.00
		hmac_csr_aliasing	4.170s	2072.428us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	76.130s	14081.119us	1	1	100.00
V2	back_pressure	hmac_back_pressure	65.510s	2462.940us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	207.280s	7581.059us	1	1	100.00
		hmac_test_sha384_vectors	470.100s	53938.125us	1	1	100.00
		hmac_test_sha512_vectors	18.940s	922.021us	1	1	100.00
		hmac_test_hmac256_vectors	7.080s	263.700us	1	1	100.00
		hmac_test_hmac384_vectors	6.210s	2895.988us	1	1	100.00
		hmac_test_hmac512_vectors	9.020s	1220.624us	1	1	100.00
V2	burst_wr	hmac_burst_wr	3.560s	404.595us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	674.310s	5436.242us	1	1	100.00
V2	error	hmac_error	8.100s	682.058us	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	92.920s	2440.520us	1	1	100.00
V2	save_and_restore	hmac_smoke	10.020s	1826.028us	1	1	100.00
		hmac_long_msg	76.130s	14081.119us	1	1	100.00
		hmac_back_pressure	65.510s	2462.940us	1	1	100.00
		hmac_datapath_stress	674.310s	5436.242us	1	1	100.00
		hmac_burst_wr	3.560s	404.595us	1	1	100.00
		hmac_stress_all	13.750s	1390.846us	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	10.020s	1826.028us	1	1	100.00
		hmac_long_msg	76.130s	14081.119us	1	1	100.00
		hmac_back_pressure	65.510s	2462.940us	1	1	100.00
		hmac_datapath_stress	674.310s	5436.242us	1	1	100.00
		hmac_wipe_secret	92.920s	2440.520us	1	1	100.00
		hmac_test_sha256_vectors	207.280s	7581.059us	1	1	100.00
		hmac_test_sha384_vectors	470.100s	53938.125us	1	1	100.00
		hmac_test_sha512_vectors	18.940s	922.021us	1	1	100.00
		hmac_test_hmac256_vectors	7.080s	263.700us	1	1	100.00
		hmac_test_hmac384_vectors	6.210s	2895.988us	1	1	100.00
		hmac_test_hmac512_vectors	9.020s	1220.624us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	10.020s	1826.028us	1	1	100.00
		hmac_long_msg	76.130s	14081.119us	1	1	100.00
		hmac_back_pressure	65.510s	2462.940us	1	1	100.00
		hmac_datapath_stress	674.310s	5436.242us	1	1	100.00
		hmac_burst_wr	3.560s	404.595us	1	1	100.00
		hmac_error	8.100s	682.058us	1	1	100.00
		hmac_wipe_secret	92.920s	2440.520us	1	1	100.00
		hmac_test_sha256_vectors	207.280s	7581.059us	1	1	100.00
		hmac_test_sha384_vectors	470.100s	53938.125us	1	1	100.00
		hmac_test_sha512_vectors	18.940s	922.021us	1	1	100.00
		hmac_test_hmac256_vectors	7.080s	263.700us	1	1	100.00
		hmac_test_hmac384_vectors	6.210s	2895.988us	1	1	100.00
		hmac_test_hmac512_vectors	9.020s	1220.624us	1	1	100.00
		hmac_stress_all	13.750s	1390.846us	1	1	100.00
V2	stress_all	hmac_stress_all	13.750s	1390.846us	1	1	100.00
V2	alert_test	hmac_alert_test	0.560s	159.952us	1	1	100.00
V2	intr_test	hmac_intr_test	0.710s	51.605us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.400s	209.910us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.400s	209.910us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.880s	16.329us	1	1	100.00
		hmac_csr_rw	0.760s	92.330us	1	1	100.00
		hmac_csr_aliasing	4.170s	2072.428us	1	1	100.00
		hmac_same_csr_outstanding	1.430s	105.353us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.880s	16.329us	1	1	100.00
		hmac_csr_rw	0.760s	92.330us	1	1	100.00
		hmac_csr_aliasing	4.170s	2072.428us	1	1	100.00
		hmac_same_csr_outstanding	1.430s	105.353us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	1.120s	350.398us	1	1	100.00
		hmac_tl_intg_err	3.130s	1426.810us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.130s	1426.810us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	10.020s	1826.028us	1	1	100.00
V3	stress_reset	hmac_stress_reset	1.550s	147.303us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	42.440s	33762.292us	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.810s	120.227us	1	1	100.00
		TOTAL			28	28	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.56	99.63	95.73	100.00	91.18	99.17	96.42	44.77