I2C Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	25.880s	11968.537us	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.580s	726.765us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.920s	23.960us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.650s	17.331us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.660s	1040.925us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.570s	42.756us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.000s	49.369us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.650s	17.331us	1	1	100.00
		i2c_csr_aliasing	1.570s	42.756us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.250s	11.215us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.000s	0.000us	0	1	0.00
V2	host_maxperf	i2c_host_perf	55.980s	28404.822us	1	1	100.00
V2	host_override	i2c_host_override	0.970s	29.425us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	46.170s	2703.666us	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	68.230s	3129.288us	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.580s	154.233us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.330s	734.284us	1	1	100.00
		i2c_host_fifo_reset_rx	4.290s	198.749us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	108.080s	5828.916us	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	18.430s	5036.270us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.260s	550.732us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.940s	518.378us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	123.940s	38861.578us	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.370s	1830.224us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	13.960s	2626.664us	1	1	100.00
		i2c_target_intr_smoke	4.250s	3879.460us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.180s	340.374us	1	1	100.00
		i2c_target_fifo_reset_tx	1.930s	257.645us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.390s	12446.007us	1	1	100.00
		i2c_target_stress_rd	13.960s	2626.664us	1	1	100.00
		i2c_target_intr_stress_wr	39.970s	22881.945us	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.210s	9567.206us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	100.980s	3436.001us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	10.600s	2457.961us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.880s	10213.161us	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.670s	3983.394us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.460s	231.073us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	55.980s	28404.822us	1	1	100.00
		i2c_host_perf_precise	72.660s	2560.367us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	18.430s	5036.270us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.850s	716.621us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.130s	1266.783us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.900s	1836.472us	1	1	100.00
		i2c_target_nack_txstretch	2.060s	525.238us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	8.960s	693.425us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.570s	1040.329us	1	1	100.00
V2	alert_test	i2c_alert_test	0.760s	50.273us	1	1	100.00
V2	intr_test	i2c_intr_test	0.750s	18.375us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.550s	69.035us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.550s	69.035us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.920s	23.960us	1	1	100.00
		i2c_csr_rw	0.650s	17.331us	1	1	100.00
		i2c_csr_aliasing	1.570s	42.756us	1	1	100.00
		i2c_same_csr_outstanding	1.100s	61.841us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.920s	23.960us	1	1	100.00
		i2c_csr_rw	0.650s	17.331us	1	1	100.00
		i2c_csr_aliasing	1.570s	42.756us	1	1	100.00
		i2c_same_csr_outstanding	1.100s	61.841us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.560s	172.329us	1	1	100.00
		i2c_sec_cm	1.070s	1433.540us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.560s	172.329us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.210s	3498.660us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.260s	108.511us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.890s	895.861us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.90	96.41	84.86	89.24	44.64	92.33	96.19	76.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.10146190757192869633917679189410274015445483978084950522428967491927639123381
      Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3498660392 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3498660392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.24581390014126852805346148056951901034963681661454791322464689915809558170770
      Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 895860908 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 895860908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.48609357244193276813585992122305346488719542815649770396193146984781349340398
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  11215362 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  11215362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.15208632389341134401176712349314936842697629412092947899989418622317113331202
      Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.47409326794809180874287423045354583567390346821443447831256884277220190575703
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 518378051 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 518378051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.23684013962728081478140739118604674822376701093468455698537739372850238659666
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 108511254 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 108511254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.110992503483498396891111021681525577611658137482611128572136782540425315656818
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10213161379 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10213161379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---