KEYMGR Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.070s	186.283us	1	1	100.00
V1	random	keymgr_random	21.770s	1154.004us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.960s	34.326us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.160s	15.269us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.170s	264.597us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.960s	1792.683us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.630s	174.719us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.160s	15.269us	1	1	100.00
		keymgr_csr_aliasing	10.960s	1792.683us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	9.860s	268.084us	1	1	100.00
V2	sideload	keymgr_sideload	14.080s	1706.200us	1	1	100.00
		keymgr_sideload_kmac	3.070s	170.021us	1	1	100.00
		keymgr_sideload_aes	2.550s	72.784us	1	1	100.00
		keymgr_sideload_otbn	2.090s	226.367us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.960s	146.577us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	9.280s	1013.542us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.860s	218.317us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.340s	1691.772us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.710s	121.487us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.600s	128.679us	1	1	100.00
V2	stress_all	keymgr_stress_all	39.180s	2570.034us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.900s	12.974us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.730s	15.183us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.180s	90.320us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.180s	90.320us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.960s	34.326us	1	1	100.00
		keymgr_csr_rw	1.160s	15.269us	1	1	100.00
		keymgr_csr_aliasing	10.960s	1792.683us	1	1	100.00
		keymgr_same_csr_outstanding	2.160s	96.875us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.960s	34.326us	1	1	100.00
		keymgr_csr_rw	1.160s	15.269us	1	1	100.00
		keymgr_csr_aliasing	10.960s	1792.683us	1	1	100.00
		keymgr_same_csr_outstanding	2.160s	96.875us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
		keymgr_tl_intg_err	3.980s	193.053us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.730s	403.069us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.730s	403.069us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.730s	403.069us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.730s	403.069us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.560s	138.487us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.980s	193.053us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.730s	403.069us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	9.860s	268.084us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	21.770s	1154.004us	1	1	100.00
		keymgr_csr_rw	1.160s	15.269us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	21.770s	1154.004us	1	1	100.00
		keymgr_csr_rw	1.160s	15.269us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	21.770s	1154.004us	1	1	100.00
		keymgr_csr_rw	1.160s	15.269us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	9.280s	1013.542us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.710s	121.487us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.710s	121.487us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	21.770s	1154.004us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.720s	35.622us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.630s	160.155us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	9.280s	1013.542us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.630s	160.155us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.630s	160.155us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.630s	160.155us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.170s	1653.995us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.630s	160.155us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.050s	440.875us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.57	98.66	94.04	91.36	86.05	97.67	97.48	61.71

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.41603900455023523094493665783188261205451287437980021396104856511796388614426
      Line 636, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 440875194 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 440875194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---