KMAC/MASKED Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	24.110s	5153.883us	2	2	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.920s	34.959us	2	2	100.00
V1	csr_rw	kmac_csr_rw	0.790s	17.759us	2	2	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.440s	623.306us	2	2	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.210s	178.882us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.900s	71.387us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.790s	17.759us	2	2	100.00
		kmac_csr_aliasing	5.210s	178.882us	2	2	100.00
V1	mem_walk	kmac_mem_walk	0.880s	13.787us	2	2	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.260s	39.175us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3007.820s	476366.795us	2	2	100.00
V2	burst_write	kmac_burst_write	960.940s	62176.760us	2	2	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1872.480s	79327.958us	2	2	100.00
		kmac_test_vectors_sha3_256	1081.180s	70089.570us	2	2	100.00
		kmac_test_vectors_sha3_384	1437.470s	69229.120us	2	2	100.00
		kmac_test_vectors_sha3_512	10.710s	1503.035us	1	2	50.00
		kmac_test_vectors_shake_128	1383.430s	20731.189us	2	2	100.00
		kmac_test_vectors_shake_256	1066.470s	32747.940us	2	2	100.00
		kmac_test_vectors_kmac	1.780s	148.233us	2	2	100.00
		kmac_test_vectors_kmac_xof	2.180s	97.891us	2	2	100.00
V2	sideload	kmac_sideload	214.860s	5459.548us	2	2	100.00
V2	app	kmac_app	200.220s	16021.537us	2	2	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	122.900s	8614.308us	2	2	100.00
V2	entropy_refresh	kmac_entropy_refresh	75.330s	10744.030us	2	2	100.00
V2	error	kmac_error	271.710s	60996.771us	2	2	100.00
V2	key_error	kmac_key_error	8.500s	20727.493us	2	2	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.670s	65.429us	2	2	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.140s	574.135us	2	2	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.810s	133.412us	2	2	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	51.710s	23833.236us	2	2	100.00
V2	lc_escalation	kmac_lc_escalation	1.560s	58.060us	2	2	100.00
V2	stress_all	kmac_stress_all	1052.950s	37579.215us	2	2	100.00
V2	intr_test	kmac_intr_test	0.770s	20.536us	2	2	100.00
V2	alert_test	kmac_alert_test	0.900s	14.994us	2	2	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.290s	373.157us	2	2	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.290s	373.157us	2	2	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.920s	34.959us	2	2	100.00
		kmac_csr_rw	0.790s	17.759us	2	2	100.00
		kmac_csr_aliasing	5.210s	178.882us	2	2	100.00
		kmac_same_csr_outstanding	1.780s	280.159us	2	2	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.920s	34.959us	2	2	100.00
		kmac_csr_rw	0.790s	17.759us	2	2	100.00
		kmac_csr_aliasing	5.210s	178.882us	2	2	100.00
		kmac_same_csr_outstanding	1.780s	280.159us	2	2	100.00
V2		TOTAL			51	52	98.08
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.870s	159.657us	2	2	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.870s	159.657us	2	2	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.870s	159.657us	2	2	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.870s	159.657us	2	2	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	379.196us	2	2	100.00
V2S	tl_intg_err	kmac_tl_intg_err	3.440s	1010.396us	2	2	100.00
		kmac_sec_cm	70.100s	26945.517us	2	2	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.440s	1010.396us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.560s	58.060us	2	2	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	24.110s	5153.883us	2	2	100.00
V2S	sec_cm_key_sideload	kmac_sideload	214.860s	5459.548us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.870s	159.657us	2	2	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	70.100s	26945.517us	2	2	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	70.100s	26945.517us	2	2	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	70.100s	26945.517us	2	2	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	24.110s	5153.883us	2	2	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.560s	58.060us	2	2	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	70.100s	26945.517us	2	2	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	120.310s	33174.566us	2	2	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	24.110s	5153.883us	2	2	100.00
V2S		TOTAL			10	10	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	85.590s	3300.313us	1	2	50.00
V3		TOTAL			1	2	50.00
		TOTAL			78	80	97.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.25	99.00	93.63	99.70	66.20	96.83	95.81	94.57

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.68308824655101987213083391881968500631826005401967925090652633780039602116408
      Line 302, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3300312764 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 3300312764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_512 has 1 failures.

    • 0.kmac_test_vectors_sha3_512.22531719901929377880887105793599281745761455027858888492683544061953442899615
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log

        UVM_ERROR @ 101263273 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 101263273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---